From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 21 Nov 2018 15:11:28 +0000 (+0000)
Subject: convert case statement
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6bba190794140001bb515d2b4085b31a89731a41;p=rv32.git

convert case statement
---

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index a120573..f35e68c 100644
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -46,65 +46,53 @@ class CPUFetchStage(Module):
         self.output_pc = Signal(32, reset=reset_vector)
         self.output_instruction = Signal(32)
         output reg `fetch_output_state output_state
-        
+
         self.comb += [
             self.cd_sys.clk.eq(self.clk),
             self.cd_sys.rst.eq(self.reset)
         ]
 
         fetch_pc = Signal(32, reset=reset_vector)
-        
+
         self.sync += output_pc.eq((fetch_action == `fetch_action_wait) ? output_pc : fetch_pc);
-        
-        memory_interface_fetch_address = fetch_pc[31:2];
+
+        memory_interface_fetch_address = fetch_pc[2:]
 
         initial output_pc <= reset_vector;
         initial output_state <= `fetch_output_state_empty;
-        
+
         delayed_instruction = Signal(32, reset=0);
         delayed_instruction_valid = Signal(reset=0);
-        
+
         self.sync += delayed_instruction.eq(output_instruction)
-        
-        assign output_instruction = delayed_instruction_valid ? delayed_instruction : memory_interface_fetch_data;
-        
+        self.sync += output_state.eq(fetch_output_state_empty)
+
+        self.comb += output_instruction.eq(delayed_instruction_valid ? delayed_instruction : memory_interface_fetch_data)
+
         self.sync += delayed_instruction_valid.eq(fetch_action == `fetch_action_wait)
-        
-        always @(posedge clk or posedge reset) begin
-            if(reset) begin
-                output_state <= `fetch_output_state_empty;
-            end
-            else begin
-                case(fetch_action)
-                `fetch_action_default,
-                `fetch_action_ack_trap: begin
-                    if(memory_interface_fetch_valid) begin
-                        fetch_pc <= fetch_pc + 4;
-                        output_state <= `fetch_output_state_valid;
-                    end
-                    else begin
-                        fetch_pc <= mtvec;
-                        output_state <= `fetch_output_state_trap;
-                    end
-                end
-                `fetch_action_fence: begin
-                    fetch_pc <= output_pc + 4;
-                    output_state <= `fetch_output_state_empty;
-                end
-                `fetch_action_jump: begin
-                    fetch_pc <= target_pc;
-                    output_state <= `fetch_output_state_empty;
-                end
-                `fetch_action_error_trap,
-                `fetch_action_noerror_trap: begin
-                    fetch_pc <= mtvec;
-                    output_state <= `fetch_output_state_empty;
-                end
-                `fetch_action_wait: begin
-                    fetch_pc <= fetch_pc;
-                    output_state <= `fetch_output_state_valid;
-                end
-                endcase
-            end
-        end
-    endmodule
+
+        fc = {}
+        self.comb += Case(fetch_action, fc)
+        fc[fetch_action_ack_trap] =
+                If(memory_interface_fetch_valid,
+                   [fetch_pc.eq(fetch_pc + 4),
+                    output_state.eq(fetch_output_state_valid)]
+                ).Else(
+                   [fetch_pc.eq(mtvec),
+                    output_state.eq(fetch_output_state_trap)]
+                )
+        fc[fetch_action_default] = fc[fetch_action_ack_trap]
+        fc[fetch_action_fence] =
+                [ fetch_pc.eq(output_pc + 4),
+                  output_state.eq(fetch_output_state_empty)]
+        fc[fetch_action_jump] =
+                [ fetch_pc.eq(target_pc),
+                  output_state.eq(fetch_output_state_empty)]
+        fc[fetch_action_error_trap] =
+                   [fetch_pc.eq(mtvec),
+                    output_state.eq(fetch_output_state_empty)]
+        fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
+        fc[fetch_action_wait] =
+                   [fetch_pc.eq(fetch_pc),
+                    output_state.eq(fetch_output_state_valid)]
+