From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 24 Feb 2014 11:41:25 +0000 (+0100)
Subject: Don't blow up constants unneccessarily in Verilog frontend
X-Git-Tag: yosys-0.3.0~107
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6bc94b7eb2ecc7c2836c2fc10029542ce92eae11;p=yosys.git

Don't blow up constants unneccessarily in Verilog frontend
---

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index bc3783bda..dda069cb8 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -906,7 +906,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				detectSignWidth(width_hint, sign_hint);
 
 			is_signed = sign_hint;
-			return RTLIL::SigSpec(bitsAsConst(width_hint, sign_hint));
+			return RTLIL::SigSpec(bitsAsConst());
 		}
 
 	// simply return the corresponding RTLIL::SigSpec for an AST_IDENTIFIER node