From: Ron Dreslinski <rdreslin@umich.edu>
Date: Tue, 11 Jul 2006 19:42:31 +0000 (-0400)
Subject: Fix ordering issue with squashed Icache Fetches and Static data in packet.
X-Git-Tag: m5_2.0_beta1~36^2~2^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6bcc65c1f866348f64a804a8bcc1f6dc06145afa;p=gem5.git

Fix ordering issue with squashed Icache Fetches and Static data in packet.

Now hello world works with 2 levels of cache with O3 CPU(multiple outstanding requests).

src/cpu/o3/fetch_impl.hh:
    Fix ordering issue with squashed Icache Fetches and Static data in packet.

--HG--
extra : convert_revision : a6adb87540b007ead0b4982cb3f31da8199fb5ca
---

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index de883b5ba..39a13f9f8 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -357,6 +357,8 @@ DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
         return;
     }
 
+    memcpy(cacheData[tid], pkt->getPtr<uint8_t *>(), cacheBlkSize);
+
     if (!drainPending) {
         // Wake up the CPU (if it went to sleep and was waiting on
         // this completion event).
@@ -548,7 +550,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
         // Build packet here.
         PacketPtr data_pkt = new Packet(mem_req,
                                         Packet::ReadReq, Packet::Broadcast);
-        data_pkt->dataStatic(cacheData[tid]);
+        data_pkt->dataDynamic(new uint8_t[cacheBlkSize]);
 
         DPRINTF(Fetch, "Fetch: Doing instruction read.\n");