From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Mon, 29 Jun 2020 12:24:33 +0000 (+0200)
Subject: Add -Wall to simulations
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6bd7b759d1fafa153edade2e2e042939f05b3beb;p=gram.git

Add -Wall to simulations
---

diff --git a/gram/simulation/runsimcrg.sh b/gram/simulation/runsimcrg.sh
index 226f409..8491311 100755
--- a/gram/simulation/runsimcrg.sh
+++ b/gram/simulation/runsimcrg.sh
@@ -4,5 +4,5 @@ set -e
 LIB_DIR=/usr/local/diamond/3.11_x64/ispfpga/verilog/data/ecp5u
 
 python simcrg.py generate simcrg.v
-iverilog -o simcrg simcrgtb.v simcrg.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/CLKDIVF.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v
+iverilog -Wall -o simcrg simcrgtb.v simcrg.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/CLKDIVF.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v
 vvp simcrg -vcd
diff --git a/gram/simulation/runsimsoc.sh b/gram/simulation/runsimsoc.sh
index 53d6b02..2fd6c64 100755
--- a/gram/simulation/runsimsoc.sh
+++ b/gram/simulation/runsimsoc.sh
@@ -4,7 +4,7 @@ set -e
 LIB_DIR=/usr/local/diamond/3.11_x64/ispfpga/verilog/data/ecp5u
 
 python simsoc.py
-iverilog -g2012 -s simsoctb -o simsoc simsoctb.v build/top.debug.v dram_model/ddr3.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
+iverilog -Wall -g2012 -s simsoctb -o simsoc simsoctb.v build/top.debug.v dram_model/ddr3.v ${LIB_DIR}/ECLKSYNCB.v ${LIB_DIR}/EHXPLLL.v ${LIB_DIR}/PUR.v ${LIB_DIR}/GSR.v \
 	${LIB_DIR}/FD1S3AX.v ${LIB_DIR}/SGSR.v ${LIB_DIR}/ODDRX2F.v ${LIB_DIR}/ODDRX2DQA.v ${LIB_DIR}/DELAYF.v ${LIB_DIR}/BB.v ${LIB_DIR}/OB.v ${LIB_DIR}/IB.v \
 	${LIB_DIR}/DQSBUFM.v ${LIB_DIR}/UDFDL5_UDP_X.v ${LIB_DIR}/TSHX2DQSA.v ${LIB_DIR}/TSHX2DQA.v ${LIB_DIR}/ODDRX2DQSB.v ${LIB_DIR}/IDDRX2DQA.v DDRDLLA.patched.v \
 	${LIB_DIR}/CLKDIVF.v