From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 28 Feb 2020 12:19:10 +0000 (+0100)
Subject: interconnect/axi: set default data_width/address_width to 32-bit.
X-Git-Tag: 24jan2021_ls180~624
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6be7e9c33d6fd7e983d18c3717066b8e0137985e;p=litex.git

interconnect/axi: set default data_width/address_width to 32-bit.
---

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 534a0cca..7816315b 100644
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -56,7 +56,7 @@ def r_description(data_width, id_width):
     ]
 
 class AXIInterface(Record):
-    def __init__(self, data_width, address_width, id_width=1, clock_domain="sys"):
+    def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys"):
         self.data_width    = data_width
         self.address_width = address_width
         self.id_width      = id_width
@@ -89,7 +89,7 @@ def r_lite_description(data_width):
     ]
 
 class AXILiteInterface(Record):
-    def __init__(self, data_width, address_width, clock_domain="sys"):
+    def __init__(self, data_width=32, address_width=32, clock_domain="sys"):
         self.data_width    = data_width
         self.address_width = address_width
         self.clock_domain  = clock_domain