From: lkcl <lkcl@web>
Date: Wed, 5 Aug 2020 11:32:08 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~2290
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6bea1ad0efebc27414680f5f1cc00984c3284dfd;p=libreriscv.git

---

diff --git a/lkcl.mdwn b/lkcl.mdwn
index 4c37ade64..c4929be70 100644
--- a/lkcl.mdwn
+++ b/lkcl.mdwn
@@ -22,7 +22,6 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=346> test core to regfiles
  - <https://bugs.libre-soc.org/show_bug.cgi?id=323> MUL pipe
  - <https://bugs.libre-soc.org/show_bug.cgi?id=419> MUL proof
- - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
  - <https://bugs.libre-soc.org/show_bug.cgi?id=420> DIV proof
  - <https://bugs.libre-soc.org/show_bug.cgi?id=336> Compunit RA=0 test
  - <https://bugs.libre-soc.org/show_bug.cgi?id=345> POWER9 regfiles
@@ -56,6 +55,7 @@ move things along from one stage to the next
  - <https://bugs.libre-soc.org/show_bug.cgi?id=344> add mtmsrd
  - <https://bugs.libre-soc.org/show_bug.cgi?id=409> illegal instructions
  - <https://bugs.libre-soc.org/show_bug.cgi?id=435> MSR and PC "state"
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=324> DIV pipe
 
 ## Submitted for NLNet RFP