From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 4 Oct 2019 23:45:36 +0000 (-0700)
Subject: Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again
X-Git-Tag: working-ls180~1011
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6bf7114bbd4075c2761a478406e02d4b23742aab;p=yosys.git

Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index ded1cd60e..bd2fd91a3 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3554,6 +3554,12 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
 	if (width_ != other.width_)
 		return false;
 
+	// Without this, SigSpec() == SigSpec(State::S0, 0) will fail
+	//   since the RHS will contain one SigChunk of width 0 causing
+	//   the size check below to fail
+	if (width_ == 0)
+		return true;
+
 	pack();
 	other.pack();