From: lkcl Date: Sat, 23 Oct 2021 21:57:07 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~3542 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6bfd0ecac46b52d95547b24cb2ff12b387fc5404;p=libreriscv.git --- diff --git a/3d_gpu/architecture/dynamic_simd/slice.mdwn b/3d_gpu/architecture/dynamic_simd/slice.mdwn index 4b3c7e21c..035af9aad 100644 --- a/3d_gpu/architecture/dynamic_simd/slice.mdwn +++ b/3d_gpu/architecture/dynamic_simd/slice.mdwn @@ -175,7 +175,7 @@ take signal a, of 16 bits, each bit being numbered in hexadecimal: | | | AfAeAdAc AbAaA9A8 A7A6A5A4 A3A2A1A0 -and take a slice a[0:1] to create 3-bit values, where padding is +and take a slice a[0:2] to create 3-bit values, where padding is specified by "x", at each elwid: elwid | | | @@ -187,17 +187,17 @@ The presence of "x" unused portions actually requires some additional partition points: elwid | | | | | | | - 0b00 x x x x x x x x x x x x x A2A1A0 - 0b01 x x x x x AaA9A8 x x x x x A2A1A0 - 0b10 x AeAdAc x AaA9A8 x A6A5A4 x A2A1A0 + 0b00 x x x x x x x x x x x x x|A2A1A0 + 0b01 x x x x |x|AaA9A8|x x x x x|A2A1A0 + 0b10 x|AeAdAc|x|AaA9A8|x|A6A5A4|x|A2A1A0 Now let us take a signal, b, of 2-bit lengths, and attempt to perform an add operation: elwid | | | - 0b00 x x x x x x B1B0 - 0b01 x x B5B4 x x B1B0 - 0b10 B7B6 B5B4 B3B2 B1B0 + 0b00 x x x x x x |B1B0 + 0b01 x x |B5B4|x x |B1B0 + 0b10 B7B6|B5B4|B3B2 B1B0 This is not immediately possible (at least not obviously so) and consequently b needs expanding @@ -232,4 +232,8 @@ Illustrating the case where a Sliced (fixed element width) SimdSignal is added to one which has variable-length elements that take up the entirety of the partition (overall fixed width): -(TODO: third example) + elwid | | | + 0b00 B7B6 B5B4 B3B2 B1B0 + 0b01 B7B6 B5B4|B3B2 B1B0 + 0b10 B7B6|B5B4|B3B2|B1B0 +