From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 1 Feb 2018 11:51:49 +0000 (+0100)
Subject: Fix single-bit $stable handling in verific front-end
X-Git-Tag: yosys-0.8~224
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c00e064e2024b7b41d3c32ed4cf7f0f6857506b;p=yosys.git

Fix single-bit $stable handling in verific front-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index fa1640050..09c379f19 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1150,6 +1150,28 @@ struct VerificImporter
 					continue;
 			}
 
+			if (inst->Type() == PRIM_SVA_STABLE && !mode_nosva)
+			{
+				VerificClockEdge clock_edge(this, inst->GetInput2()->Driver());
+
+				SigSpec sig_d = net_map_at(inst->GetInput1());
+				SigSpec sig_o = net_map_at(inst->GetOutput());
+				SigSpec sig_q = module->addWire(NEW_ID);
+
+				if (verbose) {
+					log("    %sedge FF with D=%s, Q=%s, C=%s.\n", clock_edge.posedge ? "pos" : "neg",
+							log_signal(sig_d), log_signal(sig_q), log_signal(clock_edge.clock_sig));
+					log("    XNOR with A=%s, B=%s, Y=%s.\n",
+							log_signal(sig_d), log_signal(sig_q), log_signal(sig_o));
+				}
+
+				module->addDff(NEW_ID, clock_edge.clock_sig, sig_d, sig_q, clock_edge.posedge);
+				module->addXnor(NEW_ID, sig_d, sig_q, sig_o);
+
+				if (!mode_keep)
+					continue;
+			}
+
 			if (inst->Type() == PRIM_SVA_PAST && !mode_nosva)
 			{
 				VerificClockEdge clock_edge(this, inst->GetInput2()->Driver());