From: Neel Date: Tue, 13 Mar 2018 16:44:45 +0000 (+0530) Subject: adding support for interface of SD/MMC. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c10b12bad8aeb24568dcc3078dc596a7285a6ab;p=pinmux.git adding support for interface of SD/MMC. --- diff --git a/pinmap.txt b/pinmap.txt index 882865c..3c94746 100644 --- a/pinmap.txt +++ b/pinmap.txt @@ -1,8 +1,14 @@ muxed 0 uart0_tx spi0_sclk uart2_tx uart3_tx 1 uart0_rx spi0_mosi uart2_rx uart3_rx -2 twi0_sda spi0_ss +2 twi0_sda spi0_ss 3 twi0_scl spi0_miso +8 sd0_clk sd1_clk +9 sd0_cmd sd1_cmd +10 sd0_d0 sd1_d0 +11 sd0_d1 sd1_d1 +12 sd0_d2 sd1_d2 +13 sd0_d3 sd1_d3 dedicated 4 uart1_tx 5 uart1_rx diff --git a/src/actual_pinmux.py b/src/actual_pinmux.py index 02603a9..2c1d76f 100644 --- a/src/actual_pinmux.py +++ b/src/actual_pinmux.py @@ -11,7 +11,10 @@ dictionary = { "spi_ss" : "output", "spi_miso" : "input", "twi_sda" : "inout", - "twi_scl" : "inout" + "twi_scl" : "inout", + "sd_clk": "output", + "sd_cmd": "output", + "sd_d": "inout", } @@ -57,11 +60,10 @@ for cell in muxed_cells: x = dictionary.get(temp) if(x is None): print( - "Error: The signal : " + + "ERROR: The signal : " + str(cell[i + 1]) + - " in lineno: " + - str(lineno) + "of pinmap.txt isn't present in the \ - current dictionary.\nUpdate dictionary or fix-typo.") + " of pinmap.txt isn't present in the current dictionary.\ + \nUpdate dictionary or fix-typo.") exit(1) if(x == "input"): pinmux = pinmux + \ diff --git a/src/interface_decl.py b/src/interface_decl.py index 826614d..8c390dd 100644 --- a/src/interface_decl.py +++ b/src/interface_decl.py @@ -39,4 +39,21 @@ twiinterface_decl = ''' (*always_ready,always_enabled*) method Action scl{0}_outen (Bit#(1) in); (*always_ready,always_enabled*) method Bit#(1) scl{0}_in; ''' + +sdinterface_decl = ''' + (*always_ready,always_enabled*) method Action sd{0}_clk (Bit#(1) in); + (*always_ready,always_enabled*) method Action sd{0}_cmd (Bit#(1) in); + (*always_ready,always_enabled*) method Action sd{0}_d0_out (Bit#(1) in); + (*always_ready,always_enabled*) method Action sd{0}_d0_outen (Bit#(1) in); + (*always_ready,always_enabled*) method Bit#(1) sd{0}_d0_in; + (*always_ready,always_enabled*) method Action sd{0}_d1_out (Bit#(1) in); + (*always_ready,always_enabled*) method Action sd{0}_d1_outen (Bit#(1) in); + (*always_ready,always_enabled*) method Bit#(1) sd{0}_d1_in; + (*always_ready,always_enabled*) method Action sd{0}_d2_out (Bit#(1) in); + (*always_ready,always_enabled*) method Action sd{0}_d2_outen (Bit#(1) in); + (*always_ready,always_enabled*) method Bit#(1) sd{0}_d2_in; + (*always_ready,always_enabled*) method Action sd{0}_d3_out (Bit#(1) in); + (*always_ready,always_enabled*) method Action sd{0}_d3_outen (Bit#(1) in); + (*always_ready,always_enabled*) method Bit#(1) sd{0}_d3_in; +''' # ======================================= # diff --git a/src/interface_def.py b/src/interface_def.py index 209cb7a..acf0d9f 100644 --- a/src/interface_def.py +++ b/src/interface_def.py @@ -55,4 +55,41 @@ twiinterface_def = ''' method scl{0}_in=wrtwi{0}_scl_in; ''' + +sdinterface_def = ''' + method Action sd{0}_clk (Bit#(1) in); + wrsd{0}_clk<=in; + endmethod + method Action sd{0}_cmd (Bit#(1) in); + wrsd{0}_cmd<=in; + endmethod + method Action sd{0}_d0_out (Bit#(1) in); + wrsd{0}_d0_out<=in; + endmethod + method Action sd{0}_d0_outen (Bit#(1) in); + wrsd{0}_d0_outen<=in; + endmethod + method sd{0}_d0_in=wrsd{0}_d0_in; + method Action sd{0}_d1_out (Bit#(1) in); + wrsd{0}_d1_out<=in; + endmethod + method Action sd{0}_d1_outen (Bit#(1) in); + wrsd{0}_d1_outen<=in; + endmethod + method sd{0}_d1_in=wrsd{0}_d1_in; + method Action sd{0}_d2_out (Bit#(1) in); + wrsd{0}_d2_out<=in; + endmethod + method Action sd{0}_d2_outen (Bit#(1) in); + wrsd{0}_d2_outen<=in; + endmethod + method sd{0}_d2_in=wrsd{0}_d2_in; + method Action sd{0}_d3_out (Bit#(1) in); + wrsd{0}_d3_out<=in; + endmethod + method Action sd{0}_d3_outen (Bit#(1) in); + wrsd{0}_d3_outen<=in; + endmethod + method sd{0}_d3_in=wrsd{0}_d3_in; +''' # ============================================== # diff --git a/src/parse.py b/src/parse.py index cd4a3fe..ed7a970 100644 --- a/src/parse.py +++ b/src/parse.py @@ -5,6 +5,7 @@ N_MUX_IO = 0 N_UART = 4 N_SPI = 1 N_TWI = 2 +N_SD = 2 # ================ # @@ -28,6 +29,7 @@ for lineno, line in enumerate(pinmapfile): dedicated_cells.append(line1) if(len(line1) > 2): muxed_cells.append(line1) +pinnumbers = sorted(pinnumbers) # ============================================= # # ======= Multiple checks to see if the user has not screwed ======# missing_pins = missing_numbers(pinnumbers) diff --git a/src/pinmux_generator.py b/src/pinmux_generator.py index 8b25d9e..11c2593 100644 --- a/src/pinmux_generator.py +++ b/src/pinmux_generator.py @@ -104,6 +104,11 @@ for i in range(0, N_TWI): bsv_file.write(''' // interface declaration between TWI-{0} and pinmux'''.format(i)) bsv_file.write(twiinterface_decl.format(i)) + +for i in range(0, N_SD): + bsv_file.write(''' + // interface declaration between SD-{0} and pinmux'''.format(i)) + bsv_file.write(sdinterface_decl.format(i)) # ============================================================== # ===== finish interface definition and start module definition======= @@ -145,6 +150,12 @@ for i in range(0, N_TWI): '''\n // following wires capture signals to IO CELL if twi-{0} is // allotted to it'''.format(i)) bsv_file.write(twiwires.format(i)) + +for i in range(0, N_SD): + bsv_file.write( + '''\n // following wires capture signals to IO CELL if sd-{0} is + // allotted to it'''.format(i)) + bsv_file.write(sdwires.format(i)) bsv_file.write("\n") # ==================================================================== # ========================= Actual pinmuxing ========================# @@ -168,6 +179,8 @@ for i in range(0, N_SPI): bsv_file.write(spiinterface_def.format(i)) for i in range(0, N_TWI): bsv_file.write(twiinterface_def.format(i)) +for i in range(0, N_SD): + bsv_file.write(sdinterface_def.format(i)) bsv_file.write(footer) print("BSV file successfully generated: bsv_src/pinmux.bsv") # ====================================================================== diff --git a/src/wire_def.py b/src/wire_def.py index da5fbef..b1a2f69 100644 --- a/src/wire_def.py +++ b/src/wire_def.py @@ -50,4 +50,45 @@ twiwires = ''' pullup_en:0, pulldown_en:0, pushpull_en:0, drivestrength:0, opendrain_en:0}}; ''' + +sdwires = ''' + Wire#(Bit#(1)) wrsd{0}_clk <-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_cmd <-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_d0_out<-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_d0_outen<-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_d0_in<-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_d1_out<-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_d1_outen<-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_d1_in<-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_d2_out<-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_d2_outen<-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_d2_in<-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_d3_out<-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_d3_outen<-mkDWire(0); + Wire#(Bit#(1)) wrsd{0}_d3_in<-mkDWire(0); + GenericIOType sd{0}_clk_io = GenericIOType{{outputval:wrsd{0}_clk, + output_en:1, input_en:0, + pullup_en:0, pulldown_en:0, pushpull_en:0, drivestrength:0, + opendrain_en:0}}; + GenericIOType sd{0}_cmd_io = GenericIOType{{outputval:wrsd{0}_cmd, + output_en:1, input_en:0, + pullup_en:0, pulldown_en:0, pushpull_en:0, drivestrength:0, + opendrain_en:0}}; + GenericIOType sd{0}_d0_io = GenericIOType{{outputval:wrsd{0}_d0_out, + output_en:wrsd{0}_d0_outen, input_en:~wrsd{0}_d0_outen, + pullup_en:0, pulldown_en:0, pushpull_en:0, drivestrength:0, + opendrain_en:0}}; + GenericIOType sd{0}_d1_io = GenericIOType{{outputval:wrsd{0}_d1_out, + output_en:wrsd{0}_d1_outen, input_en:~wrsd{0}_d1_outen, + pullup_en:0, pulldown_en:0, pushpull_en:0, drivestrength:0, + opendrain_en:0}}; + GenericIOType sd{0}_d2_io = GenericIOType{{outputval:wrsd{0}_d2_out, + output_en:wrsd{0}_d2_outen, input_en:~wrsd{0}_d2_outen, + pullup_en:0, pulldown_en:0, pushpull_en:0, drivestrength:0, + opendrain_en:0}}; + GenericIOType sd{0}_d3_io = GenericIOType{{outputval:wrsd{0}_d3_out, + output_en:wrsd{0}_d3_outen, input_en:~wrsd{0}_d3_outen, + pullup_en:0, pulldown_en:0, pushpull_en:0, drivestrength:0, + opendrain_en:0}}; +''' # =================================== #