From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 15 Mar 2018 14:15:40 +0000 (+0000)
Subject: move todo page
X-Git-Tag: convert-csv-opcode-to-binary~5776
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c15338d6713aa8c5bdc50b3565b3930e2da1848;p=libreriscv.git

move todo page
---

diff --git a/shakti/m_class/todo.mdwn b/shakti/m_class/todo.mdwn
new file mode 100644
index 000000000..3b7db751e
--- /dev/null
+++ b/shakti/m_class/todo.mdwn
@@ -0,0 +1,29 @@
+# TODO list summary
+
+See diagram:
+[[shakti_libre_riscv.jpg]]
+
+## RISC-V team
+
+* RV64GC SMP Core
+* Analyse and decide L1 / L2 cache sizes
+
+## Richard Herveille
+
+* RGB/TTL interface, AXI conversion
+
+## Rudi @ asics.ws
+
+* AC97/I2S/PCM interface
+* DDR (4-bit) UTMI-to-ULPI
+
+## TBD
+
+* 1/2/4-bit SD/MMC
+* eMMC (8-bit SD/MMC)
+* DDR3/DDR4 PHY
+* Quad SPI (down-compatible to 1-bit SPI)
+* Pinmux (underway)
+* Video Processing Block
+* 3D Engine (Nyuzi?)
+
diff --git a/shakti/todo.mdwn b/shakti/todo.mdwn
deleted file mode 100644
index 3b7db751e..000000000
--- a/shakti/todo.mdwn
+++ /dev/null
@@ -1,29 +0,0 @@
-# TODO list summary
-
-See diagram:
-[[shakti_libre_riscv.jpg]]
-
-## RISC-V team
-
-* RV64GC SMP Core
-* Analyse and decide L1 / L2 cache sizes
-
-## Richard Herveille
-
-* RGB/TTL interface, AXI conversion
-
-## Rudi @ asics.ws
-
-* AC97/I2S/PCM interface
-* DDR (4-bit) UTMI-to-ULPI
-
-## TBD
-
-* 1/2/4-bit SD/MMC
-* eMMC (8-bit SD/MMC)
-* DDR3/DDR4 PHY
-* Quad SPI (down-compatible to 1-bit SPI)
-* Pinmux (underway)
-* Video Processing Block
-* 3D Engine (Nyuzi?)
-