From: lkcl <lkcl@web>
Date: Mon, 26 Oct 2020 16:27:36 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~1947
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c1907b6fa82ebc11602079f5bddf08ddea26a3b;p=libreriscv.git

---

diff --git a/openpower/sv/predication.mdwn b/openpower/sv/predication.mdwn
index 7bc116211..9320f12f5 100644
--- a/openpower/sv/predication.mdwn
+++ b/openpower/sv/predication.mdwn
@@ -26,7 +26,7 @@ Implementation note: even in in-order microarchitectures it is strongly adviseab
 
 # Proposals
 
-## Adding new predicate register types and associated opcodes
+## Adding new predicate register file type and associated opcodes
 
 This idea, adding new predicate manipulation opcodes,
 violates the fundamental design principles of SV to not add