From: Alan Modra Date: Thu, 26 Dec 2019 05:26:25 +0000 (+1030) Subject: ubsan: v850: left shift cannot be represented in type 'int' X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c2ca6c25dbefd7192dac52e7fd156ae0f299f1f;p=binutils-gdb.git ubsan: v850: left shift cannot be represented in type 'int' Another 1 << 31 complaint. * v850-dis.c (disassemble): Avoid signed overflow. Don't use long vars when unsigned int will do. --- diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index bdbb5f74b1f..07f30e27d6b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2019-12-26 Alan Modra + + * v850-dis.c (disassemble): Avoid signed overflow. Don't use + long vars when unsigned int will do. + 2019-12-24 Alan Modra * arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var. diff --git a/opcodes/v850-dis.c b/opcodes/v850-dis.c index 45e6c65d83a..df2c2a5d39b 100644 --- a/opcodes/v850-dis.c +++ b/opcodes/v850-dis.c @@ -499,7 +499,7 @@ disassemble (bfd_vma memaddr, 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 }; int *regs; int i; - unsigned long int mask = 0; + unsigned int mask = 0; int pc = 0; switch (operand->shift) @@ -514,12 +514,12 @@ disassemble (bfd_vma memaddr, for (i = 0; i < 32; i++) { - if (value & (1 << i)) + if (value & (1u << i)) { switch (regs[ i ]) { default: - mask |= (1 << regs[ i ]); + mask |= (1u << regs[ i ]); break; case 0: /* xgettext:c-format */ @@ -543,10 +543,10 @@ disassemble (bfd_vma memaddr, int shown_one = 0; for (bit = 0; bit < 32; bit++) - if (mask & (1 << bit)) + if (mask & (1u << bit)) { - unsigned long int first = bit; - unsigned long int last; + unsigned int first = bit; + unsigned int last; if (shown_one) info->fprintf_func (info->stream, ", "); @@ -556,7 +556,7 @@ disassemble (bfd_vma memaddr, info->fprintf_func (info->stream, "%s", get_v850_reg_name (first)); for (bit++; bit < 32; bit++) - if ((mask & (1 << bit)) == 0) + if ((mask & (1u << bit)) == 0) break; last = bit;