From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 22 Jun 2019 00:44:21 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/xaig' into xc7mux
X-Git-Tag: working-ls180~1208^2~95
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c2cb519965ac9b4057a90cd46f474c092967be2;p=yosys.git

Merge remote-tracking branch 'origin/xaig' into xc7mux
---

6c2cb519965ac9b4057a90cd46f474c092967be2
diff --cc CHANGELOG
index 51ff4e1a4,192fc5a8d..18dfcf389
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -16,17 -16,15 +16,18 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "gate2lut.v" techmap rule
      - Added "rename -src"
      - Added "equiv_opt" pass
+     - Added "shregmap -tech xilinx"
      - Added "read_aiger" frontend
 +    - Added "shregmap -tech xilinx"
-     - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
      - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
      - Added "synth_xilinx -abc9" (experimental)
      - Added "synth_ice40 -abc9" (experimental)
      - Added "synth -abc9" (experimental)
++    - Added "muxpack" pass
      - Extended "muxcover -mux{4,8,16}=<cost>"
 -    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
      - Fixed sign extension of unsized constants with 'bx and 'bz MSB
-     - Added "muxpack" pass
++    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 +    - "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
  
  
  Yosys 0.7 .. Yosys 0.8