From: Luke Kenneth Casson Leighton Date: Tue, 25 Jun 2019 13:23:28 +0000 (+0100) Subject: correct reg table format X-Git-Tag: convert-csv-opcode-to-binary~4430 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c4e6e8d4474b9b692888404d8f508d25e28aaf5;p=libreriscv.git correct reg table format --- diff --git a/simple_v_extension/reg_table_format.mdwn b/simple_v_extension/reg_table_format.mdwn index 35a460828..9fd73e327 100644 --- a/simple_v_extension/reg_table_format.mdwn +++ b/simple_v_extension/reg_table_format.mdwn @@ -1,17 +1,17 @@ 16 bit format: -| RegCAM | | 15 | (14..8) | 7 | (6..5) | (4..0) | -| ------ | | - | - | - | ------ | ------- | -| 0 | | isvec0 | regidx0 | i/f | vew0 | regkey | -| 1 | | isvec1 | regidx1 | i/f | vew1 | regkey | -| .. | | isvec.. | regidx.. | i/f | vew.. | regkey | -| 15 | | isvec15 | regidx15 | i/f | vew15 | regkey | +| RegCAM | 15 | (14..8) | 7 | (6..5) | (4..0) | +| ------ | - | - | - | ------ | ------- | +| 0 | isvec0 | regidx0 | i/f | vew0 | regkey0 | +| 1 | isvec1 | regidx1 | i/f | vew1 | regkey1 | +| 2 | isvec2 | regidx2 | i/f | vew2 | regkey2 | +| 3 | isvec3 | regidx3 | i/f | vew3 | regkey3 | 8 bit format: -| RegCAM | | 7 | (6..5) | (4..0) | -| ------ | | - | ------ | ------- | -| 0 | | i/f | vew0 | regnum | +| RegCAM | 7 | (6..5) | (4..0) | +| ------ | - | ------ | ------- | +| 0 | i/f | vew0 | regnum | Showing the mapping (relationship) between 8-bit and 16-bit format: @@ -20,5 +20,5 @@ Showing the mapping (relationship) between 8-bit and 16-bit format: | 0 | isvec=1 | regnum0<<2 | i/f | vew0 | regnum0 | | 1 | isvec=1 | regnum1<<2 | i/f | vew1 | regnum1 | | 2 | isvec=1 | regnum2<<2 | i/f | vew2 | regnum2 | -| 3 | isvec=1 | regnum2<<2 | i/f | vew3 | regnum3 | +| 3 | isvec=1 | regnum3<<2 | i/f | vew3 | regnum3 |