From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 15 Jan 2019 09:55:27 +0000 (+0100)
Subject: Fix handling of $shiftx in Verilog back-end
X-Git-Tag: yosys-0.9~330
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c5049f016538e887476bb66d3f653155fa354ff;p=yosys.git

Fix handling of $shiftx in Verilog back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 2537e18e5..8da3c0627 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -709,11 +709,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 	if (cell->type == "$shiftx")
 	{
+		std::string temp_id = next_auto_id();
+		f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort("\\A"))-1, temp_id.c_str());
+		dump_sigspec(f, cell->getPort("\\A"));
+		f << stringf(";\n");
+
 		f << stringf("%s" "assign ", indent.c_str());
 		dump_sigspec(f, cell->getPort("\\Y"));
-		f << stringf(" = ");
-		dump_sigspec(f, cell->getPort("\\A"));
-		f << stringf("[");
+		f << stringf(" = %s[", temp_id.c_str());
 		if (cell->getParam("\\B_SIGNED").as_bool())
 			f << stringf("$signed(");
 		dump_sigspec(f, cell->getPort("\\B"));