From: Megan Wachs Date: Fri, 16 Feb 2018 23:49:09 +0000 (-0800) Subject: i2c: Allow irq to be cleared X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c5b80671cab9436195fc3fdde9544764a5ded34;p=sifive-blocks.git i2c: Allow irq to be cleared --- diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala index aecf2dc..d767a26 100644 --- a/src/main/scala/devices/i2c/I2C.scala +++ b/src/main/scala/devices/i2c/I2C.scala @@ -488,16 +488,16 @@ trait HasI2CModuleContents extends MultiIOModule with HasRegMap { // hack: b/c the same register offset is used to write cmd and read status val nextCmd = Wire(UInt(8.W)) - nextCmd := cmd.asUInt cmd := (new CommandBundle).fromBits(nextCmd) + nextCmd := cmd.asUInt & 0xFE.U // clear IRQ_ACK bit (essentially 1 cycle pulse b/c it is overwritten by regmap below) + // Note: This wins over the regmap update of nextCmd (even if something tries to write them to 1, these values take priority). when (cmdAck || arbLost) { cmd.start := false.B // clear command bits when done cmd.stop := false.B // or when aribitration lost cmd.read := false.B cmd.write := false.B } - cmd.irqAck := false.B // clear IRQ_ACK bit (essentially 1 cycle pulse b/c it is overwritten by regmap below) status.receivedAck := receivedAck when (stopCond) {