From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 8 May 2020 23:01:12 +0000 (+0100)
Subject: add  ALUFirstInputData
X-Git-Tag: div_pipeline~1326
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c73a1b863cec18f8da8fc2f6678511f311e39ca;p=soc.git

add  ALUFirstInputData
---

diff --git a/src/soc/alu/pipe_data.py b/src/soc/alu/pipe_data.py
index 083ca105..fe76aeb7 100644
--- a/src/soc/alu/pipe_data.py
+++ b/src/soc/alu/pipe_data.py
@@ -17,6 +17,25 @@ class IntegerData:
         return [self.ctx.eq(i.ctx)]
 
 
+class ALUFirstInputData(IntegerData):
+    def __init__(self, pspec):
+        super().__init__(pspec)
+        self.a = Signal(64, reset_less=True)
+        self.b = Signal(64, reset_less=True)
+        self.so = Signal(reset_less=True)
+
+    def __iter__(self):
+        yield from super().__iter__()
+        yield self.a
+        yield self.b
+        yield self.so
+
+    def eq(self, i):
+        lst = super().eq(i)
+        return lst + [self.a.eq(i.a), self.b.eq(i.b),
+                      self.so.eq(i.so)]
+
+
 class ALUInputData(IntegerData):
     def __init__(self, pspec):
         super().__init__(pspec)