From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 11 Oct 2023 10:57:58 +0000 (+0100)
Subject: accidentally commented-out matrix tests
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c7dad6aef97109e5427e5a46f63c36c3ad20585;p=openpower-isa.git

accidentally commented-out matrix tests
---

diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index 579617b9..aa6401aa 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -16,7 +16,7 @@ class DecoderTestCase(FHDLTestCase):
         for i in range(32):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
-    def tst_sv_remap1(self):
+    def test_sv_remap1(self):
         """>>> lst = ["svshape 2, 2, 3, 0, 0",
                         "svremap 31, 1, 2, 3, 0, 0, 0",
                        "sv.fmadds *0, *8, *16, *0"
@@ -81,7 +81,7 @@ class DecoderTestCase(FHDLTestCase):
             #    self.assertEqual(sim.fpr(i+2), t)
             #    self.assertEqual(sim.fpr(i+6), u)
 
-    def tst_sv_remap2(self):
+    def test_sv_remap2(self):
         """>>> lst = ["svshape 5, 4, 3, 0, 0",
                         "svremap 31, 1, 2, 3, 0, 0, 0",
                        "sv.fmadds *0, *8, *16, *0"