From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 15 Oct 2020 14:59:21 +0000 (+0100)
Subject: add extra variant to litex core
X-Git-Tag: 24jan2021_ls180~148
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c8ba5bea16f5067547b5bf60ec2d4520fd64e29;p=soc.git

add extra variant to litex core
---

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 9703cbfe..81bd0dfc 100644
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -13,7 +13,8 @@ from libresoc.ls180 import io
 from litex.build.generic_platform import ConstraintManager
 
 
-CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180"]
+CPU_VARIANTS = ["standard", "standard32", "standardjtag", "ls180",
+                "standardjtagnoirq"]
 
 
 def make_wb_bus(prefix, obj, simple=False):