From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Sat, 21 Mar 2015 06:11:49 +0000 (-0700)
Subject: For misaligned fetch, set mepc = addr of branch/jump
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c965e11dc7950207f7cc0baff0ff273c33f4ecc;p=riscv-isa-sim.git

For misaligned fetch, set mepc = addr of branch/jump
---

diff --git a/riscv/decode.h b/riscv/decode.h
index 2fdb042..4ad4549 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -153,7 +153,11 @@ private:
 #define sext_xlen(x) (((sreg_t)(x) << (64-xlen)) >> (64-xlen))
 #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen))
 
-#define set_pc(x) (npc = sext_xlen(x))
+#define set_pc(x) \
+  do { if ((x) & 3 /* For now... */) \
+         throw trap_instruction_address_misaligned(x); \
+       npc = sext_xlen(x); \
+     } while(0)
 
 #define validate_csr(which, write) ({ \
   unsigned my_priv = get_field(STATE.mstatus, MSTATUS_PRV); \