From: lkcl <lkcl@web>
Date: Sat, 11 Sep 2021 13:26:36 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~161
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c97ee49312a2fec73c890630b7ac5b6ae921d97;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 10d638db0..2b74dc214 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -135,7 +135,8 @@ Brief description of fields:
   Contrast this with
   normal SVP64 `sz=1` behaviour, where *only* a zero is put in
   place of masked-out predicate bits.
-* **sz=0** When `sz=0` skipping occurs as usual, but unlike all
+* **sz=0** When `sz=0` skipping occurs as usual on
+  masked-out elements, but unlike all
   other SVP64 behaviour which entirely skips an element with
   no related side-effects at all, there are certain
   special circumstances where CTR