From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 26 May 2020 23:47:53 +0000 (+0100)
Subject: check assertions
X-Git-Tag: div_pipeline~806
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c9aef6f6baeed83b07c25eba57b87a15a6db95c;p=soc.git

check assertions
---

diff --git a/src/soc/regfile/virtual_port.py b/src/soc/regfile/virtual_port.py
index 152fb4cd..322efe8e 100644
--- a/src/soc/regfile/virtual_port.py
+++ b/src/soc/regfile/virtual_port.py
@@ -92,9 +92,10 @@ def regfile_array_sim(dut, rp1, rp2, rp3, wp):
     yield rp2.ren.eq(0)
     data1 = yield rp1.data_o
     print (data1)
+    assert data1 == 6, data1
     data2 = yield rp2.data_o
     print (data2)
-    assert data1 == 6
+    assert data2 == 2, data2
     yield
     data = yield rp1.data_o
     print (data)