From: Florent Kermarrec Date: Mon, 13 Jan 2020 15:56:31 +0000 (+0100) Subject: soc_core: fix uart stub X-Git-Tag: 24jan2021_ls180~750 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6c9f418d26c09c8fc2338d31316844f0bbea029d;p=litex.git soc_core: fix uart stub --- diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 8bd25f2c..59faef81 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -242,7 +242,7 @@ class SoCCore(Module): if uart_name in ["stub", "stream"]: self.submodules.uart = uart.UART() if uart_name == "stub": - self.comb += uart.sink.ready.eq(1) + self.comb += self.uart.sink.ready.eq(1) elif uart_name == "crossover": self.submodules.uart = uart.UARTCrossover() else: