From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Jul 2020 12:12:28 +0000 (+0100)
Subject: add slow spr regfile regspec support
X-Git-Tag: div_pipeline~162^2~66
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ca75178955b187651070276fe3588250a7cf7d7;p=soc.git

add slow spr regfile regspec support
---

diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 2fc32fe0..6f461c96 100644
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -94,7 +94,10 @@ def regspec_decode_read(e, regfile, name):
             return e.read_fast2.ok, 1<<e.read_fast2.data
 
     if regfile == 'SPR':
-        assert False, "regfile TODO %s %s" % (regfile, name)
+        # Int register numbering is *binary* encoded
+        if name == 'spr1':
+            return e.read_spr1.ok, e.read_spr1.data
+
     assert False, "regspec not found %s %s" % (regfile, name)
 
 
@@ -149,6 +152,9 @@ def regspec_decode_write(e, regfile, name):
             return e.write_fast2, 1<<e.write_fast2.data
 
     if regfile == 'SPR':
-        assert False, "regfile TODO %s %s" % (regfile, name)
+        # Int register numbering is *binary* encoded
+        if name == 'spr1': # SPR1
+            return e.write_spr, e.write_spr.data
+
     assert False, "regspec not found %s %s" % (regfile, name)
 
diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 5461eec5..74c283f3 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -136,8 +136,8 @@ class SPRRegs(RegFile):
     def __init__(self):
         n_sprs = len(SPR)
         super().__init__(64, n_sprs)
-        self.w_ports = {'spr': self.write_port(name="dest")}
-        self.r_ports = {'spr': self.read_port("src")}
+        self.w_ports = {'spr1': self.write_port(name="dest")}
+        self.r_ports = {'spr1': self.read_port("src")}
 
 
 # class containing all regfiles: int, cr, xer, fast, spr
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 0ba74997..9feafaf1 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -162,6 +162,7 @@ class TestIssuer(Elaboratable):
 
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
+             'spr': 1,
              'shiftrot': 1}
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',