From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Feb 2019 09:48:40 +0000 (+0000)
Subject: add rounding stage
X-Git-Tag: ls180-24jan2020~2014
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ca7b00bf57ffb3cb96b8b3c290057db009cd752;p=ieee754fpu.git

add rounding stage
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index bfc1c878..8c99a1ff 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -226,6 +226,7 @@ class FPADD:
 
             # ******
             # Second stage of add: preparation for normalisation.
+            # detects when tot sum is too big (tot[27] is kinda a carry bit)
 
             with m.State("add_1"):
                 m.next = "normalise_1"
@@ -284,6 +285,16 @@ class FPADD:
                 with m.Else():
                     m.next = "round"
 
+            # ******
+            # rounding stage
+
+            with m.State("round"):
+                m.next = "pack"
+                with m.If(guard & (round_bit | sticky | z_m[0])):
+                    m.d.sync += z_m.eq(z_m + 1) # mantissa rounds up
+                    with m.If(z_m == 0xffffff): # all 1s
+                        m.d.sync += z_e.eq(z_e + 1) # exponent rounds up
+
         return m
 
 """