From: Anton Blanchard Date: Wed, 11 Sep 2019 07:21:52 +0000 (+1000) Subject: SOC memory wishbone should clear ACK regardless of STB X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6cbf45638882cc37bba2429dccfbcd473bdc8147;p=microwatt.git SOC memory wishbone should clear ACK regardless of STB The memory wishbone doesn't clear ACK and move the state machine on until STB is de-asserted. This seems like it isn't compliant with the spec and results in a maximum throughput of 1 transfer every 3 cycles. Fixing this improves the situation to one transfer every 2 cycles. Signed-off-by: Anton Blanchard --- diff --git a/fpga/mw_soc_memory.vhdl b/fpga/mw_soc_memory.vhdl index 1c6fdc1..e9ace36 100644 --- a/fpga/mw_soc_memory.vhdl +++ b/fpga/mw_soc_memory.vhdl @@ -92,10 +92,8 @@ begin state <= ACK; end if; when ACK => - if wishbone_in.stb = '0' then - read_ack <= '0'; - state <= IDLE; - end if; + read_ack <= '0'; + state <= IDLE; end case; else state <= IDLE;