From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 5 Jun 2019 07:53:06 +0000 (+0200)
Subject: Indent fix
X-Git-Tag: yosys-0.9~92
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6cc60ffd67784fa74e3ccbf9c2c273ad610e14b2;p=yosys.git

Indent fix

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 5b43d528c..e46d0a1dc 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -404,29 +404,31 @@ struct SetundefPass : public Pass {
 					initwires.insert(wire);
 				}
 
-				for (int wire_types = 0; wire_types < 2; wire_types++) {
-                                        pool<SigBit> ffbitsToErase;
-                                        for (auto wire : module->wires()) {
-                                                if (wire->name[0] == (wire_types ? '\\' : '$')) {
-                                                        next_wire:
-                                                        continue;
-                                                }
-
-                                                for (auto bit : sigmap(wire))
-                                                        if (!ffbits.count(bit)) {
-                                                                goto next_wire;
-                                                        }
-
-                                                for (auto bit : sigmap(wire)) {
-                                                        ffbitsToErase.insert(bit);
-                                                }
-
-                                                initwires.insert(wire);
-                                        }
-                                        for (const auto &bit : ffbitsToErase) {
-                                                ffbits.erase(bit);
-                                        }
-                                }
+				for (int wire_types = 0; wire_types < 2; wire_types++)
+				{
+					pool<SigBit> ffbitsToErase;
+					for (auto wire : module->wires())
+					{
+						if (wire->name[0] == (wire_types ? '\\' : '$')) {
+					next_wire:
+							continue;
+						}
+
+						for (auto bit : sigmap(wire))
+							if (!ffbits.count(bit)) {
+								goto next_wire;
+							}
+
+						for (auto bit : sigmap(wire)) {
+							ffbitsToErase.insert(bit);
+						}
+
+						initwires.insert(wire);
+					}
+					for (const auto & bit : ffbitsToErase) {
+						ffbits.erase(bit);
+					}
+				}
 
 				for (auto wire : initwires)
 				{