From: Segher Boessenkool Date: Tue, 4 Jun 2019 23:35:13 +0000 (+0200) Subject: rs6000: -> p X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6cc8f68381ef967849049433c63cb6324b16a1ac;p=gcc.git rs6000: -> p We don't need the mode attribute, if we make work for V4SF and V2DF just like for SF and DF. * config/rs6000/rs6000.md (define_mode_attr sd): Add values for V4SF and V2DF. * config/rs6000/vsx.md (define_mode_attr VSs): Delete. (rest of file): Adjust. From-SVN: r271936 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 55463f0416c..3571664b160 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-06-04 Segher Boessenkool + + * config/rs6000/rs6000.md (define_mode_attr sd): Add values for V4SF + and V2DF. + * config/rs6000/vsx.md (define_mode_attr VSs): Delete. + (rest of file): Adjust. + 2019-06-04 Segher Boessenkool * config/rs6000/vsx.md (vsx_): Use wa instead of . diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 2c86082e30c..b8b246a5a2d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -493,7 +493,8 @@ (define_mode_iterator SFDF2 [SF DF]) ; A generic s/d attribute, for sp/dp for example. -(define_mode_attr sd [(SF "s") (DF "d")]) +(define_mode_attr sd [(SF "s") (DF "d") + (V4SF "s") (V2DF "d")]) ; "s" or nothing, for fmuls/fmul for example. (define_mode_attr s [(SF "s") (DF "")]) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 519f1a01ce2..4061a5e2292 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -93,20 +93,6 @@ (V1TI "vd2") (TI "vd2")]) -;; Map into the appropriate suffix based on the type -(define_mode_attr VSs [(V16QI "sp") - (V8HI "sp") - (V4SI "sp") - (V4SF "sp") - (V2DF "dp") - (V2DI "dp") - (DF "dp") - (SF "sp") - (TF "dp") - (KF "dp") - (V1TI "dp") - (TI "dp")]) - ;; Map the register class used (define_mode_attr VSr [(V16QI "v") (V8HI "v") @@ -1594,7 +1580,7 @@ (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa") (match_operand:VSX_F 2 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvadd %x0,%x1,%x2" + "xvaddp %x0,%x1,%x2" [(set_attr "type" "")]) (define_insn "*vsx_sub3" @@ -1602,7 +1588,7 @@ (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa") (match_operand:VSX_F 2 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvsub %x0,%x1,%x2" + "xvsubp %x0,%x1,%x2" [(set_attr "type" "")]) (define_insn "*vsx_mul3" @@ -1610,7 +1596,7 @@ (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa") (match_operand:VSX_F 2 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvmul %x0,%x1,%x2" + "xvmulp %x0,%x1,%x2" [(set_attr "type" "")]) ; Emulate vector with scalar for vec_mul in V2DImode @@ -1658,7 +1644,7 @@ (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa") (match_operand:VSX_F 2 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvdiv %x0,%x1,%x2" + "xvdivp %x0,%x1,%x2" [(set_attr "type" "")]) ; Emulate vector with scalar for vec_div in V2DImode @@ -1790,7 +1776,7 @@ (match_operand:VSX_B 2 "vsx_register_operand" "wa")] UNSPEC_VSX_TDIV))] "VECTOR_UNIT_VSX_P (mode)" - "xtdiv %0,%x1,%x2" + "xtdivp %0,%x1,%x2" [(set_attr "type" "")]) (define_insn "vsx_fre2" @@ -1798,21 +1784,21 @@ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")] UNSPEC_FRES))] "VECTOR_UNIT_VSX_P (mode)" - "xvre %x0,%x1" + "xvrep %x0,%x1" [(set_attr "type" "")]) (define_insn "*vsx_neg2" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa") (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvneg %x0,%x1" + "xvnegp %x0,%x1" [(set_attr "type" "")]) (define_insn "*vsx_abs2" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa") (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvabs %x0,%x1" + "xvabsp %x0,%x1" [(set_attr "type" "")]) (define_insn "vsx_nabs2" @@ -1821,7 +1807,7 @@ (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa"))))] "VECTOR_UNIT_VSX_P (mode)" - "xvnabs %x0,%x1" + "xvnabsp %x0,%x1" [(set_attr "type" "")]) (define_insn "vsx_smax3" @@ -1829,7 +1815,7 @@ (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa") (match_operand:VSX_F 2 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvmax %x0,%x1,%x2" + "xvmaxp %x0,%x1,%x2" [(set_attr "type" "")]) (define_insn "*vsx_smin3" @@ -1837,14 +1823,14 @@ (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa") (match_operand:VSX_F 2 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvmin %x0,%x1,%x2" + "xvminp %x0,%x1,%x2" [(set_attr "type" "")]) (define_insn "*vsx_sqrt2" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa") (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvsqrt %x0,%x1" + "xvsqrtp %x0,%x1" [(set_attr "type" "")]) (define_insn "*vsx_rsqrte2" @@ -1852,7 +1838,7 @@ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")] UNSPEC_RSQRT))] "VECTOR_UNIT_VSX_P (mode)" - "xvrsqrte %x0,%x1" + "xvrsqrtep %x0,%x1" [(set_attr "type" "")]) ;; *tsqrt* returning the fg flag @@ -1886,7 +1872,7 @@ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "wa")] UNSPEC_VSX_TSQRT))] "VECTOR_UNIT_VSX_P (mode)" - "xtsqrt %0,%x1" + "xtsqrtp %0,%x1" [(set_attr "type" "")]) ;; Fused vector multiply/add instructions. Support the classical Altivec @@ -1928,8 +1914,8 @@ (match_operand:VSX_F 3 "vsx_register_operand" "0,wa"))))] "VECTOR_UNIT_VSX_P (mode)" "@ - xvmsuba %x0,%x1,%x2 - xvmsubm %x0,%x1,%x3" + xvmsubap %x0,%x1,%x2 + xvmsubmp %x0,%x1,%x3" [(set_attr "type" "")]) (define_insn "*vsx_nfma4" @@ -1941,8 +1927,8 @@ (match_operand:VSX_F 3 "vsx_register_operand" "0,wa"))))] "VECTOR_UNIT_VSX_P (mode)" "@ - xvnmadda %x0,%x1,%x2 - xvnmaddm %x0,%x1,%x3" + xvnmaddap %x0,%x1,%x2 + xvnmaddmp %x0,%x1,%x3" [(set_attr "type" "")]) (define_insn "*vsx_nfmsv4sf4" @@ -1980,7 +1966,7 @@ (eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa") (match_operand:VSX_F 2 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvcmpeq %x0,%x1,%x2" + "xvcmpeqp %x0,%x1,%x2" [(set_attr "type" "")]) (define_insn "vsx_gt" @@ -1988,7 +1974,7 @@ (gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa") (match_operand:VSX_F 2 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvcmpgt %x0,%x1,%x2" + "xvcmpgtp %x0,%x1,%x2" [(set_attr "type" "")]) (define_insn "*vsx_ge" @@ -1996,7 +1982,7 @@ (ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa") (match_operand:VSX_F 2 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvcmpge %x0,%x1,%x2" + "xvcmpgep %x0,%x1,%x2" [(set_attr "type" "")]) ;; Compare vectors producing a vector result and a predicate, setting CR6 to @@ -2011,7 +1997,7 @@ (eq:VSX_F (match_dup 1) (match_dup 2)))] "VECTOR_UNIT_VSX_P (mode)" - "xvcmpeq. %x0,%x1,%x2" + "xvcmpeqp. %x0,%x1,%x2" [(set_attr "type" "")]) (define_insn "*vsx_gt__p" @@ -2024,7 +2010,7 @@ (gt:VSX_F (match_dup 1) (match_dup 2)))] "VECTOR_UNIT_VSX_P (mode)" - "xvcmpgt. %x0,%x1,%x2" + "xvcmpgtp. %x0,%x1,%x2" [(set_attr "type" "")]) (define_insn "*vsx_ge__p" @@ -2037,7 +2023,7 @@ (ge:VSX_F (match_dup 1) (match_dup 2)))] "VECTOR_UNIT_VSX_P (mode)" - "xvcmpge. %x0,%x1,%x2" + "xvcmpgep. %x0,%x1,%x2" [(set_attr "type" "")]) ;; Vector select @@ -2071,7 +2057,7 @@ (match_operand:VSX_F 2 "vsx_register_operand" "wa")] UNSPEC_COPYSIGN))] "VECTOR_UNIT_VSX_P (mode)" - "xvcpsgn %x0,%x2,%x1" + "xvcpsgnp %x0,%x2,%x1" [(set_attr "type" "")]) ;; For the conversions, limit the register class for the integer value to be @@ -2084,52 +2070,52 @@ [(set (match_operand:VSX_F 0 "gpc_reg_operand" "=wa") (float:VSX_F (match_operand: 1 "gpc_reg_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvcvsx %x0,%x1" + "xvcvsxp %x0,%x1" [(set_attr "type" "")]) (define_insn "vsx_floatuns2" [(set (match_operand:VSX_F 0 "gpc_reg_operand" "=wa") (unsigned_float:VSX_F (match_operand: 1 "gpc_reg_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvcvux %x0,%x1" + "xvcvuxp %x0,%x1" [(set_attr "type" "")]) (define_insn "vsx_fix_trunc2" [(set (match_operand: 0 "gpc_reg_operand" "=wa") (fix: (match_operand:VSX_F 1 "gpc_reg_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xcvsxs %x0,%x1" + "xcvpsxs %x0,%x1" [(set_attr "type" "")]) (define_insn "vsx_fixuns_trunc2" [(set (match_operand: 0 "gpc_reg_operand" "=wa") (unsigned_fix: (match_operand:VSX_F 1 "gpc_reg_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xcvuxs %x0,%x1" + "xcvpuxs %x0,%x1" [(set_attr "type" "")]) ;; Math rounding functions -(define_insn "vsx_xri" +(define_insn "vsx_xrpi" [(set (match_operand:VSX_B 0 "vsx_register_operand" "=wa") (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "wa")] UNSPEC_VSX_ROUND_I))] "VECTOR_UNIT_VSX_P (mode)" - "xri %x0,%x1" + "xrpi %x0,%x1" [(set_attr "type" "")]) -(define_insn "vsx_xric" +(define_insn "vsx_xrpic" [(set (match_operand:VSX_B 0 "vsx_register_operand" "=wa") (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "wa")] UNSPEC_VSX_ROUND_IC))] "VECTOR_UNIT_VSX_P (mode)" - "xric %x0,%x1" + "xrpic %x0,%x1" [(set_attr "type" "")]) (define_insn "vsx_btrunc2" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa") (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xvriz %x0,%x1" + "xvrpiz %x0,%x1" [(set_attr "type" "")]) (define_insn "*vsx_b2trunc2" @@ -2137,7 +2123,7 @@ (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "wa")] UNSPEC_FRIZ))] "VECTOR_UNIT_VSX_P (mode)" - "xriz %x0,%x1" + "xrpiz %x0,%x1" [(set_attr "type" "")]) (define_insn "vsx_floor2" @@ -2145,7 +2131,7 @@ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")] UNSPEC_FRIM))] "VECTOR_UNIT_VSX_P (mode)" - "xvrim %x0,%x1" + "xvrpim %x0,%x1" [(set_attr "type" "")]) (define_insn "vsx_ceil2" @@ -2153,7 +2139,7 @@ (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")] UNSPEC_FRIP))] "VECTOR_UNIT_VSX_P (mode)" - "xvrip %x0,%x1" + "xvrpip %x0,%x1" [(set_attr "type" "")]) @@ -4688,47 +4674,47 @@ [(set_attr "type" "fpcompare")]) ;; VSX Vector Extract Exponent Double and Single Precision -(define_insn "xvxexp" +(define_insn "xvxexpp" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa") (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")] UNSPEC_VSX_VXEXP))] "TARGET_P9_VECTOR" - "xvxexp %x0,%x1" + "xvxexpp %x0,%x1" [(set_attr "type" "vecsimple")]) ;; VSX Vector Extract Significand Double and Single Precision -(define_insn "xvxsig" +(define_insn "xvxsigp" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa") (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa")] UNSPEC_VSX_VXSIG))] "TARGET_P9_VECTOR" - "xvxsig %x0,%x1" + "xvxsigp %x0,%x1" [(set_attr "type" "vecsimple")]) ;; VSX Vector Insert Exponent Double and Single Precision -(define_insn "xviexp" +(define_insn "xviexpp" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa") (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" "wa") (match_operand:VSX_F 2 "vsx_register_operand" "wa")] UNSPEC_VSX_VIEXP))] "TARGET_P9_VECTOR" - "xviexp %x0,%x1,%x2" + "xviexpp %x0,%x1,%x2" [(set_attr "type" "vecsimple")]) ;; VSX Vector Test Data Class Double and Single Precision ;; The corresponding elements of the result vector are all ones ;; if any of the conditions tested by operand 3 are satisfied. -(define_insn "xvtstdc" +(define_insn "xvtstdcp" [(set (match_operand: 0 "vsx_register_operand" "=wa") (unspec: [(match_operand:VSX_F 1 "vsx_register_operand" "wa") (match_operand:SI 2 "u7bit_cint_operand" "n")] UNSPEC_VSX_VTSTDC))] "TARGET_P9_VECTOR" - "xvtstdc %x0,%x1,%2" + "xvtstdcp %x0,%x1,%2" [(set_attr "type" "vecsimple")]) ;; ISA 3.0 String Operations Support