From: Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Date: Thu, 17 Aug 2017 19:31:54 +0000 (+0000)
Subject: altivec.md (UNSPEC_VMRGOW_DIRECT): New constant.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ccd2ece2f5232e6fa2d6ebb4227ca03af77b87b;p=gcc.git

altivec.md (UNSPEC_VMRGOW_DIRECT): New constant.

2017-08-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/altivec.md (UNSPEC_VMRGOW_DIRECT): New constant.
	(p8_vmrgew_v4sf_direct): Generalize to p8_vmrgew_<mode>_direct.
	(p8_vmrgow_<mode>_direct): New define_insn.
	* config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Properly
	handle endianness for vmrgew and vmrgow permute patterns.

From-SVN: r251161
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3ef90cf6efb..17b49295d4e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2017-08-17  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>
+
+	* config/rs6000/altivec.md (UNSPEC_VMRGOW_DIRECT): New constant.
+	(p8_vmrgew_v4sf_direct): Generalize to p8_vmrgew_<mode>_direct.
+	(p8_vmrgow_<mode>_direct): New define_insn.
+	* config/rs6000/rs6000.c (altivec_expand_vec_perm_const): Properly
+	handle endianness for vmrgew and vmrgow permute patterns.
+
 2017-08-17  Peter Bergner  <bergner@vnet.ibm.com>
 
 	* config/rs6000/altivec.md (VParity): Remove TARGET_VSX_TIMODE.
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index e9c209df52f..c9dddda1b4c 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -148,6 +148,7 @@
    UNSPEC_VMRGL_DIRECT
    UNSPEC_VSPLT_DIRECT
    UNSPEC_VMRGEW_DIRECT
+   UNSPEC_VMRGOW_DIRECT
    UNSPEC_VSUMSWS_DIRECT
    UNSPEC_VADDCUQ
    UNSPEC_VADDEUQM
@@ -1357,15 +1358,24 @@
 }
   [(set_attr "type" "vecperm")])
 
-(define_insn "p8_vmrgew_v4sf_direct"
-  [(set (match_operand:V4SF 0 "register_operand" "=v")
-	(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
-		      (match_operand:V4SF 2 "register_operand" "v")]
+(define_insn "p8_vmrgew_<mode>_direct"
+  [(set (match_operand:VSX_W 0 "register_operand" "=v")
+	(unspec:VSX_W [(match_operand:VSX_W 1 "register_operand" "v")
+		       (match_operand:VSX_W 2 "register_operand" "v")]
 		     UNSPEC_VMRGEW_DIRECT))]
   "TARGET_P8_VECTOR"
   "vmrgew %0,%1,%2"
   [(set_attr "type" "vecperm")])
 
+(define_insn "p8_vmrgow_<mode>_direct"
+  [(set (match_operand:VSX_W 0 "register_operand" "=v")
+	(unspec:VSX_W [(match_operand:VSX_W 1 "register_operand" "v")
+		       (match_operand:VSX_W 2 "register_operand" "v")]
+		     UNSPEC_VMRGOW_DIRECT))]
+  "TARGET_P8_VECTOR"
+  "vmrgow %0,%1,%2"
+  [(set_attr "type" "vecperm")])
+
 (define_expand "vec_widen_umult_even_v16qi"
   [(use (match_operand:V8HI 0 "register_operand" ""))
    (use (match_operand:V16QI 1 "register_operand" ""))
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index c35c5641c4e..b31b1ab460f 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -35282,9 +35282,13 @@ altivec_expand_vec_perm_const (rtx operands[4])
       (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
        : CODE_FOR_altivec_vmrghw_direct),
       {  8,  9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
-    { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgew_v4si,
+    { OPTION_MASK_P8_VECTOR,
+      (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
+       : CODE_FOR_p8_vmrgow_v4sf_direct),
       {  0,  1,  2,  3, 16, 17, 18, 19,  8,  9, 10, 11, 24, 25, 26, 27 } },
-    { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgow,
+    { OPTION_MASK_P8_VECTOR,
+      (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
+       : CODE_FOR_p8_vmrgew_v4sf_direct),
       {  4,  5,  6,  7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
   };