From: lkcl <lkcl@web>
Date: Fri, 11 Feb 2022 13:28:59 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3214
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ccfd76b5e6050c726a441a3a8281b0e431a24ed;p=libreriscv.git

---

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 07b1380b6..c66a02366 100644
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -1,5 +1,16 @@
 # ULX3S JTAG Connection with ft232r
 
+Note: this page is for connecting a *secondary* JTAG connection to
+the Libre-SOC Core, in order to test the actual HDL implementation
+of JTAG.  "Normal" JTAG documentation instructs you how to connect
+to the **FPGA** hard-macro JTAG port (in some fashion).  Whilst the
+FPGA has a JTAG port as a hard-macro these instructions do **not**
+apply to that: they apply **specifically** to actual implementation
+in HDL of a JTAG TAP interface suitable for deployment on an ASIC,
+and, consequently, in order to test that, four GPIO pads had to be
+picked to bring those signals out.  These instructions describe how
+to correctly wire up an FT232r to connect to those four GPIO pads.
+
 Cross referenced with:
 
 <https://bugs.libre-soc.org/show_bug.cgi?id=517>