From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 25 Oct 2018 11:18:59 +0000 (+0200)
Subject: Merge pull request #679 from udif/pr_syntax_error
X-Git-Tag: yosys-0.9~431
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6cd5b8b76ba9f9df04571defa33fc862aec87924;p=yosys.git

Merge pull request #679 from udif/pr_syntax_error

More meaningful SystemVerilog/Verilog parser error messages
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6cd5b8b76ba9f9df04571defa33fc862aec87924