From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 15 Aug 2019 18:25:42 +0000 (-0700)
Subject: Fix
X-Git-Tag: working-ls180~1142^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6cd8cace0c1d2a9f7b1f1cd56a223c38a5ea799a;p=yosys.git

Fix
---

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 330c56e22..6dea611e3 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -506,7 +506,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 				did_something = true;
 			} else {
 				cover("opt.opt_expr.unary_buffer");
-				replace_cell(assign_map, module, cell, "unary_buffer", "\\Y", cell->getPort(ID(A)));
+				replace_cell(assign_map, module, cell, "unary_buffer", ID(Y), cell->getPort(ID(A)));
 			}
 			goto next_cell;
 		}
@@ -747,7 +747,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		if (cell->type.in(ID($_NOT_), ID($not), ID($logic_not)) && cell->getPort(ID(Y)).size() == 1 &&
 				invert_map.count(assign_map(cell->getPort(ID(A)))) != 0) {
 			cover_list("opt.opt_expr.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str());
-			replace_cell(assign_map, module, cell, "double_invert", ID(Y), invert_map.at(assign_map(cell->getPort(ID("A")))));
+			replace_cell(assign_map, module, cell, "double_invert", ID(Y), invert_map.at(assign_map(cell->getPort(ID(A)))));
 			goto next_cell;
 		}