From: Anton Blanchard <anton@linux.ibm.com>
Date: Sun, 13 Oct 2019 03:41:53 +0000 (+1100)
Subject: Fix clk_gen_bypass
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6cdb8ca9f515b5b1e4d9617d8d98548d77d04546;p=microwatt.git

Fix clk_gen_bypass

clk_gen_bypass needed updating after the addition of CLK_INPUT_HZ and
CLK_OUTPUT_HZ.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
---

diff --git a/fpga/clk_gen_bypass.vhd b/fpga/clk_gen_bypass.vhd
index d583159..a3b2df4 100644
--- a/fpga/clk_gen_bypass.vhd
+++ b/fpga/clk_gen_bypass.vhd
@@ -2,6 +2,11 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 entity clock_generator is
+    generic (
+        CLK_INPUT_HZ  : positive := 50000000;
+        CLK_OUTPUT_HZ : positive := 50000000
+        );
+
   port (
     ext_clk        : in  std_logic;
     pll_rst_in   : in  std_logic;
@@ -13,8 +18,8 @@ end entity clock_generator;
 architecture bypass of clock_generator is
 
 begin
+    assert CLK_INPUT_HZ = CLK_OUTPUT_HZ severity FAILURE;
 
-  pll_locked_out <= not pll_rst_in;
-  pll_clk_out <= ext_clk;
-
+    pll_locked_out <= not pll_rst_in;
+    pll_clk_out <= ext_clk;
 end architecture bypass;