From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Jun 2019 06:13:06 +0000 (+0100)
Subject: rename packed field to fail-on-first
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6cdc3ccc66772468f612c06ad543fee99f73a1d5;p=riscv-isa-sim.git

rename packed field to fail-on-first
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index f84aa8f..a30c2e3 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -478,7 +478,7 @@ void state_t::sv_csr_pred_unpack()
         r->regidx = c->b.regidx;
         r->zero   = c->b.zero;
         r->inv    = c->b.inv;
-        r->packed = c->b.packed;
+        r->ffirst = c->b.ffirst;
         r->active = true;
         fprintf(stderr, "setting PREDCFG %d type:%d zero:%d %d %d\n",
                         i, c->b.type, r->zero, (int)idx, (int)r->regidx);
diff --git a/riscv/sv.h b/riscv/sv.h
index 3df72d2..3b6c2e8 100644
--- a/riscv/sv.h
+++ b/riscv/sv.h
@@ -8,8 +8,8 @@
 // useful macros for constructing SV reg and predicate CSR CAM entries
 #define SV_REG_CSR(type, regkey, elwidth, regidx, isvec) \
   (regkey | (elwidth<<5) | (type<<7) | (regidx<<8) | (isvec<<15))
-#define SV_PRED_CSR(type, regkey, zero, inv, regidx, packed) \
-  (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (packed<<15))
+#define SV_PRED_CSR(type, regkey, zero, inv, regidx, ffirst) \
+  (regkey | (zero<<5) | (inv<<6) | (type<<7) | (regidx<<8) | (ffirst<<15))
 
 // this table is for the CSRs (4? for RV32E, 16 for other types)
 // it's a CAM that's used to generate 2 tables (below)
@@ -55,7 +55,7 @@ union sv_pred_csr_entry {
         unsigned int inv   : 1; // inversion=1
         unsigned int type  : 1; // 1=INT, 0=FP
         uint64_t     regidx: 7; // 7 bits
-        unsigned int packed : 1; // Packed SIMD=1
+        unsigned int ffirst: 1; // Fail on first
     } b;
     unsigned short u;
 };
@@ -66,7 +66,7 @@ typedef struct {
     unsigned int inv   : 1; // inversion=1
     uint64_t     regidx: 7; // 7 bits
     unsigned int active: 1; // enabled=1, disabled=0
-    unsigned int packed : 1; // Packed SIMD=1
+    unsigned int ffirst: 1; // Fail on first
 } sv_pred_entry;
 
 bool sv_check_reg(bool intreg, uint64_t reg);