From: Luke Kenneth Casson Leighton Date: Mon, 18 Jul 2022 20:10:59 +0000 (+0100) Subject: move another function in ISACaller (check_write) X-Git-Tag: sv_maxu_works-initial~243 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ce79aaee984c0a0d1bad013316a588829201136;p=openpower-isa.git move another function in ISACaller (check_write) --- diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index a509c2d7..f9e26604 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1559,6 +1559,14 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): self.handle_comparison(results, regnum) # any modified return results? + yield from self.check_write(info, output_names, results) + + nia_update = (yield from self.check_step_increment(results, rc_en, + asmop, ins_name)) + if nia_update: + self.update_pc_next() + + def check_write(self, info, output_names, results): if info.write_regs: for name, output in zip(output_names, results): if name == 'overflow': # ignore, done already (above) @@ -1589,7 +1597,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): # temporary hack for not having 2nd output regnum = yield getattr(self.decoder, name) is_vec = False - if self.is_svp64_mode and pred_dst_zero: + if self.is_svp64_mode and self.pred_dst_zero: log('zeroing reg %d %s' % (regnum, str(output)), is_vec) output = SelectableInt(0, 256) @@ -1607,11 +1615,6 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): else: self.gpr[regnum] = output - nia_update = (yield from self.check_step_increment(results, rc_en, - asmop, ins_name)) - if nia_update: - self.update_pc_next() - def check_step_increment(self, results, rc_en, asmop, ins_name): # check if it is the SVSTATE.src/dest step that needs incrementing # this is our Sub-Program-Counter loop from 0 to VL-1