From: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Date: Mon, 20 Jul 2020 11:47:19 +0000 (+0200)
Subject: radv: disable CPU caching for the upload BO to reduce fetch latency
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6ced98c94e28b41cc63ec94d4bdfec99d71db598;p=mesa.git

radv: disable CPU caching for the upload BO to reduce fetch latency

AMDGPU_GEM_CREATE_CPU_GTT_USWC should be faster when CPU reads
are unexpected (because they aren't cached).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5978>
---

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4b14e1ed0af..4130a62d3f9 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -483,7 +483,8 @@ radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer,
 				       RADEON_DOMAIN_GTT,
 				       RADEON_FLAG_CPU_ACCESS|
 				       RADEON_FLAG_NO_INTERPROCESS_SHARING |
-				       RADEON_FLAG_32BIT,
+				       RADEON_FLAG_32BIT |
+				       RADEON_FLAG_GTT_WC,
 				       RADV_BO_PRIORITY_UPLOAD_BUFFER);
 
 	if (!bo) {