From: whitequark <whitequark@whitequark.org>
Date: Sat, 13 Jun 2020 00:49:44 +0000 (+0000)
Subject: cxxrtl: fix rzext().
X-Git-Tag: working-ls180~474^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6cf02ed94f46d32e6116ba834894f4022fb0d407;p=yosys.git

cxxrtl: fix rzext().

This was a correctness issue, but one of the consequences is that it
resulted in jumps in generated machine code where there should have
been none. As a side effect of fixing the bug, Minerva SoC became 10%
faster.
---

diff --git a/backends/cxxrtl/cxxrtl.h b/backends/cxxrtl/cxxrtl.h
index ce21cc1e6..10184bb3f 100644
--- a/backends/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/cxxrtl.h
@@ -165,8 +165,8 @@ struct value : public expr_base<value<Bits>> {
 			carry = (shift_bits == 0) ? 0
 				: data[n] >> (chunk::bits - shift_bits);
 		}
-		if (carry != 0)
-			result.data[result.chunks - 1] = carry;
+		if (shift_chunks + chunks < result.chunks)
+			result.data[shift_chunks + chunks] = carry;
 		return result;
 	}