From: Staf Verhaegen Date: Wed, 20 May 2020 16:44:06 +0000 (+0200) Subject: Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d05b7a3f253cb2c71a4565877b19f7a4510ea14;p=libre-riscv-dev.git Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC) --- diff --git a/b9/8be2490e3018ad12c487017ad4922a90e41587 b/b9/8be2490e3018ad12c487017ad4922a90e41587 new file mode 100644 index 0000000..a8debb5 --- /dev/null +++ b/b9/8be2490e3018ad12c487017ad4922a90e41587 @@ -0,0 +1,127 @@ +Return-path: +Envelope-to: publicinbox@libre-riscv.org +Delivery-date: Wed, 20 May 2020 17:44:14 +0100 +Received: from localhost ([::1] helo=libre-riscv.org) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) + id 1jbRpF-0006Xx-PA; Wed, 20 May 2020 17:44:13 +0100 +Received: from vps2.stafverhaegen.be ([85.10.201.15]) + by libre-soc.org with esmtp (Exim 4.89) + (envelope-from ) id 1jbRpE-0006Xr-Kq + for libre-riscv-dev@lists.libre-riscv.org; Wed, 20 May 2020 17:44:12 +0100 +Received: from hpdc7800 (hpdc7800 [10.0.0.1]) + by vps2.stafverhaegen.be (Postfix) with ESMTP id 0AE5611C0459 + for ; + Wed, 20 May 2020 18:44:12 +0200 (CEST) +Message-ID: <803285a5aa4bed5be9c8d4bc5855f49174742f33.camel@fibraservi.eu> +From: Staf Verhaegen +To: libre-riscv-dev@lists.libre-riscv.org +Date: Wed, 20 May 2020 18:44:06 +0200 +In-Reply-To: +References: + <9191058ea0912f2b508a6f73ea567e5f@f-cpu.org> + + <63e8b9ce54648590e2a6fc51bc2110dde7585f5e.camel@fibraservi.eu> + +Organization: FibraServi bvba +X-Mailer: Evolution 3.28.5 (3.28.5-8.el7) +Mime-Version: 1.0 +X-Content-Filtered-By: Mailman/MimeDel 2.1.23 +Subject: Re: [libre-riscv-dev] Debug port (was Re: minimum viable ASIC) +X-BeenThere: libre-riscv-dev@lists.libre-riscv.org +X-Mailman-Version: 2.1.23 +Precedence: list +List-Id: Libre-RISCV General Development + +List-Unsubscribe: , + +List-Archive: +List-Post: +List-Help: +List-Subscribe: , + +Reply-To: Libre-RISCV General Development + +Content-Type: multipart/mixed; boundary="===============1767639589163176008==" +Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org +Sender: "libre-riscv-dev" + + +--===============1767639589163176008== +Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature"; + boundary="=-F9+HOglBJ3aN2btywKaK" + + +--=-F9+HOglBJ3aN2btywKaK +Content-Type: text/plain; charset="UTF-8" +Content-Transfer-Encoding: quoted-printable + +Luke Kenneth Casson Leighton schreef op vr 08-05-2020 om 23:19 [+0100]: +> ---crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma6= +8 +>=20 +> On Fri, May 8, 2020 at 6:23 PM Staf Verhaegen wrote: +>=20 +> ah. as a software engineer, the practice of using wildcard imports isan = +extremely bad one. i strongly advocate *not* getting into thehabit of doin= +g "from nmigen import *" everywhere - it will make yourlife - and other use= +rs lives - absolute hell when it comes to tryingto track and debug code. +> minerva has a JTAG interface as well. i corrected the practice ofusing "= +import *" in this one + +Would 'import nmigen as nm' work for you?I did not touch code for a few mon= +ths and in the mean time I do use a more PEP compliant code style. But I am= + annoyed by the individual list of things to import. For nmigen or Hurrican= +e there is typically a few lines of these includes. When I change for examp= +le a Pad to a Rectilinear I may have to update the import list. I don't see= + value add of this and it annoys me a lot.So I am thinking of switching to = +'import Hurricane as hur' and 'import nmigen as nm'To me the only valid rea= +son for not using wild cards is that a later wild card import may replace s= +omething you did import before; this is avoided by namespacing the import w= +ith 'import ... as ...'. +> it looks like the minerva team got a long way with that. alsoprovided a = +wishbone master interface: +> https://git.libre-soc.org/?p=3Dsoc.git;a=3Dblob;f=3Dsrc/soc/minerva/units= +/debug/wbmaster.py;h=3Ddb02af95b4eb3ef8ac25b348f3abaa2bcbe7d96f;hb=3Da54adc= +b65bad37b398b11e33a824c7d08c5fe509 + +That code seems to focus on the debugging protocol over the JTAG interface = +the lower level part seems to be missing.In debug/top.py:... +# FIXME: figure out where JTAGTap is +# from jtagtap import JTAGTap + + +class JTAGTap: + def __init__(self): + raise NotImplementedError( + "jtagtap package not found: figure out where JTAGTap is") +... + +My JTAG interface does actually the low level part, the protocol has to be = +done by the user on top of it. I do think I have a flexible way of adding e= +xtra shift registers and jtag commands. I also do provide boundary scan for= + the IO pins which should make PCB testing much easier (BTW, this was actua= +lly the original use case for JTAG). +greets,Staf. + + + +--=-F9+HOglBJ3aN2btywKaK-- + + + +--===============1767639589163176008== +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: base64 +Content-Disposition: inline + +X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz +Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn +Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj +di1kZXYK + +--===============1767639589163176008==-- + + +