From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Thu, 25 Jun 2020 11:47:43 +0000 (+0200)
Subject: Add rddata_en, wrdata_mask tests
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d098eb6ec440ac0a0422520d6c725ee37a52544;p=gram.git

Add rddata_en, wrdata_mask tests
---

diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py
index 64c183d..a14bb20 100644
--- a/gram/test/test_dfii.py
+++ b/gram/test/test_dfii.py
@@ -50,6 +50,7 @@ class PhaseInjectorTestCase(FHDLTestCase):
             self.assertTrue((yield dfi.phases[0].ras_n))
             self.assertTrue((yield dfi.phases[0].we_n))
             self.assertTrue((yield dfi.phases[0].act_n))
+            self.assertFalse((yield dfi.phases[0].wrdata_mask))
 
         runSimulation(m, process, "test_phaseinjector.vcd")
 
@@ -95,5 +96,21 @@ class PhaseInjectorTestCase(FHDLTestCase):
             yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
             self.assertEqual((yield pc.cnt), 2)
 
+        runSimulation(m, process, "test_phaseinjector.vcd")
+
+    def test_rddata_en(self):
+        m, dfi, csrhost = self.generate_phaseinjector()
+
+        m.submodules.pc = pc = PulseCounter()
+        m.d.comb += pc.i.eq(dfi.phases[0].rddata_en)
+
+        def process():
+            yield from wb_write(csrhost.bus, PI_COMMAND_ADDR >> 2, (1 << 5), sel=0xF)
+            yield
+            yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
+            self.assertEqual((yield pc.cnt), 1)
+            yield
+            yield from wb_write(csrhost.bus, PI_COMMAND_ISSUE_ADDR >> 2, 1, sel=0xF)
+            self.assertEqual((yield pc.cnt), 2)
 
         runSimulation(m, process, "test_phaseinjector.vcd")