From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 22 Mar 2023 21:44:28 +0000 (-0700)
Subject: convert tables to be wider rather than taller
X-Git-Tag: opf_rfc_ls001_v3~105
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d0a49899a217dd73637aa7e0473e391be4de1c3;p=libreriscv.git

convert tables to be wider rather than taller
---

diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index 50d0dccae..3531cde82 100644
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -275,24 +275,16 @@ Special Registers altered:
 
 ### Assembly Aliases
 
-| Assembly Alias       | Full Instruction       |
-|----------------------|------------------------|
-| `fcvtfgw FRT, RB`    | `fcvtfg FRT, RB, 0, 0` |
-| `fcvtfgw. FRT, RB`   | `fcvtfg FRT, RB, 0, 1` |
-| `fcvtfgws FRT, RB`   | `fcvtfg FRT, RB, 0, 2` |
-| `fcvtfgws. FRT, RB`  | `fcvtfg FRT, RB, 0, 3` |
-| `fcvtfguw FRT, RB`   | `fcvtfg FRT, RB, 1, 0` |
-| `fcvtfguw. FRT, RB`  | `fcvtfg FRT, RB, 1, 1` |
-| `fcvtfguws FRT, RB`  | `fcvtfg FRT, RB, 1, 2` |
-| `fcvtfguws. FRT, RB` | `fcvtfg FRT, RB, 1, 3` |
-| `fcvtfgd FRT, RB`    | `fcvtfg FRT, RB, 2, 0` |
-| `fcvtfgd. FRT, RB`   | `fcvtfg FRT, RB, 2, 1` |
-| `fcvtfgds FRT, RB`   | `fcvtfg FRT, RB, 2, 2` |
-| `fcvtfgds. FRT, RB`  | `fcvtfg FRT, RB, 2, 3` |
-| `fcvtfgud FRT, RB`   | `fcvtfg FRT, RB, 3, 0` |
-| `fcvtfgud. FRT, RB`  | `fcvtfg FRT, RB, 3, 1` |
-| `fcvtfguds FRT, RB`  | `fcvtfg FRT, RB, 3, 2` |
-| `fcvtfguds. FRT, RB` | `fcvtfg FRT, RB, 3, 3` |
+| Assembly Alias       | Full Instruction       |&nbsp;| Assembly Alias       | Full Instruction       |
+|----------------------|------------------------|------|----------------------|------------------------|
+| `fcvtfgw FRT, RB`    | `fcvtfg FRT, RB, 0, 0` |&nbsp;| `fcvtfgd FRT, RB`    | `fcvtfg FRT, RB, 2, 0` |
+| `fcvtfgw. FRT, RB`   | `fcvtfg FRT, RB, 0, 1` |&nbsp;| `fcvtfgd. FRT, RB`   | `fcvtfg FRT, RB, 2, 1` |
+| `fcvtfgws FRT, RB`   | `fcvtfg FRT, RB, 0, 2` |&nbsp;| `fcvtfgds FRT, RB`   | `fcvtfg FRT, RB, 2, 2` |
+| `fcvtfgws. FRT, RB`  | `fcvtfg FRT, RB, 0, 3` |&nbsp;| `fcvtfgds. FRT, RB`  | `fcvtfg FRT, RB, 2, 3` |
+| `fcvtfguw FRT, RB`   | `fcvtfg FRT, RB, 1, 0` |&nbsp;| `fcvtfgud FRT, RB`   | `fcvtfg FRT, RB, 3, 0` |
+| `fcvtfguw. FRT, RB`  | `fcvtfg FRT, RB, 1, 1` |&nbsp;| `fcvtfgud. FRT, RB`  | `fcvtfg FRT, RB, 3, 1` |
+| `fcvtfguws FRT, RB`  | `fcvtfg FRT, RB, 1, 2` |&nbsp;| `fcvtfguds FRT, RB`  | `fcvtfg FRT, RB, 3, 2` |
+| `fcvtfguws. FRT, RB` | `fcvtfg FRT, RB, 1, 3` |&nbsp;| `fcvtfguds. FRT, RB` | `fcvtfg FRT, RB, 3, 3` |
 
 
 ----------
@@ -584,25 +576,16 @@ Special Registers altered:
 
 For brevity, `[o]` is used to mean `o` is optional there.
 
-| Assembly Alias               | Full Instruction               |
-|------------------------------|--------------------------------|
-| `fcvttgw[o] RT, FRB, CVM`    | `fcvttg[o] RT, FRB, CVM, 0, 0` |
-| `fcvttgw[o]. RT, FRB, CVM`   | `fcvttg[o] RT, FRB, CVM, 0, 1` |
-| `fcvtstgw[o] RT, FRB, CVM`   | `fcvttg[o] RT, FRB, CVM, 0, 2` |
-| `fcvtstgw[o]. RT, FRB, CVM`  | `fcvttg[o] RT, FRB, CVM, 0, 3` |
-| `fcvttguw[o] RT, FRB, CVM`   | `fcvttg[o] RT, FRB, CVM, 1, 0` |
-| `fcvttguw[o]. RT, FRB, CVM`  | `fcvttg[o] RT, FRB, CVM, 1, 1` |
-| `fcvtstguw[o] RT, FRB, CVM`  | `fcvttg[o] RT, FRB, CVM, 1, 2` |
-| `fcvtstguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 3` |
-| `fcvttgd[o] RT, FRB, CVM`    | `fcvttg[o] RT, FRB, CVM, 2, 0` |
-| `fcvttgd[o]. RT, FRB, CVM`   | `fcvttg[o] RT, FRB, CVM, 2, 1` |
-| `fcvtstgd[o] RT, FRB, CVM`   | `fcvttg[o] RT, FRB, CVM, 2, 2` |
-| `fcvtstgd[o]. RT, FRB, CVM`  | `fcvttg[o] RT, FRB, CVM, 2, 3` |
-| `fcvttgud[o] RT, FRB, CVM`   | `fcvttg[o] RT, FRB, CVM, 3, 0` |
-| `fcvttgud[o]. RT, FRB, CVM`  | `fcvttg[o] RT, FRB, CVM, 3, 1` |
-| `fcvtstgud[o] RT, FRB, CVM`  | `fcvttg[o] RT, FRB, CVM, 3, 2` |
-| `fcvtstgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 3` |
-
+| Assembly Alias               | Full Instruction               | Assembly Alias               | Full Instruction               |
+|------------------------------|--------------------------------|------------------------------|--------------------------------|
+| `fcvttgw[o] RT, FRB, CVM`    | `fcvttg[o] RT, FRB, CVM, 0, 0` | `fcvttgd[o] RT, FRB, CVM`    | `fcvttg[o] RT, FRB, CVM, 2, 0` |
+| `fcvttgw[o]. RT, FRB, CVM`   | `fcvttg[o] RT, FRB, CVM, 0, 1` | `fcvttgd[o]. RT, FRB, CVM`   | `fcvttg[o] RT, FRB, CVM, 2, 1` |
+| `fcvtstgw[o] RT, FRB, CVM`   | `fcvttg[o] RT, FRB, CVM, 0, 2` | `fcvtstgd[o] RT, FRB, CVM`   | `fcvttg[o] RT, FRB, CVM, 2, 2` |
+| `fcvtstgw[o]. RT, FRB, CVM`  | `fcvttg[o] RT, FRB, CVM, 0, 3` | `fcvtstgd[o]. RT, FRB, CVM`  | `fcvttg[o] RT, FRB, CVM, 2, 3` |
+| `fcvttguw[o] RT, FRB, CVM`   | `fcvttg[o] RT, FRB, CVM, 1, 0` | `fcvttgud[o] RT, FRB, CVM`   | `fcvttg[o] RT, FRB, CVM, 3, 0` |
+| `fcvttguw[o]. RT, FRB, CVM`  | `fcvttg[o] RT, FRB, CVM, 1, 1` | `fcvttgud[o]. RT, FRB, CVM`  | `fcvttg[o] RT, FRB, CVM, 3, 1` |
+| `fcvtstguw[o] RT, FRB, CVM`  | `fcvttg[o] RT, FRB, CVM, 1, 2` | `fcvtstgud[o] RT, FRB, CVM`  | `fcvttg[o] RT, FRB, CVM, 3, 2` |
+| `fcvtstguw[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 1, 3` | `fcvtstgud[o]. RT, FRB, CVM` | `fcvttg[o] RT, FRB, CVM, 3, 3` |
 
 ----------