From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Feb 2019 22:45:04 +0000 (-0800)
Subject: Merge pull request #827 from ucb-bar/firrtlfixes
X-Git-Tag: yosys-0.9~292
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d143c9a018e5ba352a06785afeba8d50178a835;p=yosys.git

Merge pull request #827 from ucb-bar/firrtlfixes

Fix FIRRTL to Verilog process instance subfield assignment.
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6d143c9a018e5ba352a06785afeba8d50178a835