From: Michael Nolan <mtnolan2640@gmail.com>
Date: Wed, 20 May 2020 18:33:15 +0000 (-0400)
Subject: Fix small bug in op_crop
X-Git-Tag: div_pipeline~1016
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d1fa01c24bd36c0977ab67381d056e16636c881;p=soc.git

Fix small bug in op_crop
---

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index eaa3f1f6..00417651 100644
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -108,7 +108,7 @@ class CRMainStage(PipeModBase):
 
                 # Use the two input bits to look up the result in the LUT
                 idx = Signal(2, reset_less=True)
-                comb += idx.eq(Cat(cr_arr[bb], cr_arr[bb]))
+                comb += idx.eq(Cat(cr_arr[bb], cr_arr[ba]))
                 comb += cr_out_arr[bt].eq(lut[idx])
 
             ##### mtcrf #####