From: lkcl <lkcl@web>
Date: Sun, 24 Jan 2021 05:09:25 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~364
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d2ab80b68bb42415c9fcdf15bfd741e460e9e9f;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 4d2581b43..df5a14c31 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -58,7 +58,7 @@ order: listed in [[sv/overview]]
 
 ## sv.setvl
 
-a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.
+a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
 
 * ISACaller: TODO
 * power-gem5: TODO