From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 29 Sep 2015 05:12:27 +0000 (+0800)
Subject: fhdl/FullMemoryWE: fix clocking
X-Git-Tag: 24jan2021_ls180~2099^2~3^2~34
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d2d70d8796eecd7a8c0fea0c42f64303a74ba7a;p=litex.git

fhdl/FullMemoryWE: fix clocking
---

diff --git a/migen/fhdl/simplify.py b/migen/fhdl/simplify.py
index 6d91fd0e..dba41beb 100644
--- a/migen/fhdl/simplify.py
+++ b/migen/fhdl/simplify.py
@@ -41,7 +41,7 @@ class FullMemoryWE(ModuleTransformer):
                             re=port.re,
                             we_granularity=0,
                             mode=port.mode,
-                            clock_domain=port.clock)
+                            clock_domain=port.clock.cd)
                         newmem.ports.append(newport)
                         newspecials.add(newport)
                 self.replacments[orig] = newmems