From: Andrew Lukefahr <lukefahr@umich.edu>
Date: Sat, 3 Jan 2015 23:51:48 +0000 (-0600)
Subject: minor: fixed LSQ MasterPortID
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d3200440702719356ee337fc7f24075cdb75224;p=gem5.git

minor: fixed LSQ MasterPortID

Minor was reporting the data cache access as ".inst" accesses.
This just switches the MasterPortID to dataMasterPortId.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
---

diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc
index 501620746..49daa3518 100644
--- a/src/cpu/minor/lsq.cc
+++ b/src/cpu/minor/lsq.cc
@@ -1503,7 +1503,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data,
 
     request->request.setThreadContext(cpu.cpuId(), /* thread id */ 0);
     request->request.setVirt(0 /* asid */,
-        addr, size, flags, cpu.instMasterId(),
+        addr, size, flags, cpu.dataMasterId(),
         /* I've no idea why we need the PC, but give it */
         inst->pc.instAddr());