From: Adrian Herrera <adrian.herrera@arm.com>
Date: Thu, 12 Dec 2019 16:25:46 +0000 (+0000)
Subject: dev-arm: GICv3, handle GICR_ICFGR0 WI behaviour
X-Git-Tag: v19.0.0.0~147
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d37f2877ef27dcec1eb1d39e7f06b3e2386bcb8;p=gem5.git

dev-arm: GICv3, handle GICR_ICFGR0 WI behaviour

Architecture states write accesses to GICR_ICFGR0 are WI. This patch
implements handling of this behaviour instead of crashing as an invalid
offset. This is required to support certain software behaviour.

Change-Id: I1f8c57838566c360d243a925306ec35c64a920b2
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24063
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/dev/arm/gic_v3_redistributor.cc b/src/dev/arm/gic_v3_redistributor.cc
index 75fd9b326..f071c5bc7 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -579,6 +579,9 @@ Gicv3Redistributor::write(Addr addr, uint64_t data, size_t size,
 
         break;
 
+      case GICR_ICFGR0: // SGI Configuration Register
+        // WI
+        return;
       case GICR_ICFGR1: { // PPI Configuration Register
           int first_intid = Gicv3::SGI_MAX;