From: Nils Asmussen Date: Thu, 13 Feb 2020 13:15:56 +0000 (+0100) Subject: arch-riscv: show names of MiscRegs on accesses. X-Git-Tag: v20.0.0.0~119 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d3bf34a2a0cf8cd8510bd8b074bed356526531b;p=gem5.git arch-riscv: show names of MiscRegs on accesses. Printing the number of the MiscRegs makes it hard to debug problems. Therefore, this commit adds a name table and prints the name of the register. Change-Id: Icd53d5524a5d5daf3e50f253cdda56341663f26e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25649 Tested-by: kokoro Reviewed-by: Jason Lowe-Power Maintainer: Jason Lowe-Power --- diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index a71733bcb..3f1a7e1af 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -47,6 +47,133 @@ namespace RiscvISA { +const std::array MiscRegNames = {{ + [MISCREG_PRV] = "PRV", + [MISCREG_ISA] = "ISA", + [MISCREG_VENDORID] = "VENDORID", + [MISCREG_ARCHID] = "ARCHID", + [MISCREG_IMPID] = "IMPID", + [MISCREG_HARTID] = "HARTID", + [MISCREG_STATUS] = "STATUS", + [MISCREG_IP] = "IP", + [MISCREG_IE] = "IE", + [MISCREG_CYCLE] = "CYCLE", + [MISCREG_TIME] = "TIME", + [MISCREG_INSTRET] = "INSTRET", + [MISCREG_HPMCOUNTER03] = "HPMCOUNTER03", + [MISCREG_HPMCOUNTER04] = "HPMCOUNTER04", + [MISCREG_HPMCOUNTER05] = "HPMCOUNTER05", + [MISCREG_HPMCOUNTER06] = "HPMCOUNTER06", + [MISCREG_HPMCOUNTER07] = "HPMCOUNTER07", + [MISCREG_HPMCOUNTER08] = "HPMCOUNTER08", + [MISCREG_HPMCOUNTER09] = "HPMCOUNTER09", + [MISCREG_HPMCOUNTER10] = "HPMCOUNTER10", + [MISCREG_HPMCOUNTER11] = "HPMCOUNTER11", + [MISCREG_HPMCOUNTER12] = "HPMCOUNTER12", + [MISCREG_HPMCOUNTER13] = "HPMCOUNTER13", + [MISCREG_HPMCOUNTER14] = "HPMCOUNTER14", + [MISCREG_HPMCOUNTER15] = "HPMCOUNTER15", + [MISCREG_HPMCOUNTER16] = "HPMCOUNTER16", + [MISCREG_HPMCOUNTER17] = "HPMCOUNTER17", + [MISCREG_HPMCOUNTER18] = "HPMCOUNTER18", + [MISCREG_HPMCOUNTER19] = "HPMCOUNTER19", + [MISCREG_HPMCOUNTER20] = "HPMCOUNTER20", + [MISCREG_HPMCOUNTER21] = "HPMCOUNTER21", + [MISCREG_HPMCOUNTER22] = "HPMCOUNTER22", + [MISCREG_HPMCOUNTER23] = "HPMCOUNTER23", + [MISCREG_HPMCOUNTER24] = "HPMCOUNTER24", + [MISCREG_HPMCOUNTER25] = "HPMCOUNTER25", + [MISCREG_HPMCOUNTER26] = "HPMCOUNTER26", + [MISCREG_HPMCOUNTER27] = "HPMCOUNTER27", + [MISCREG_HPMCOUNTER28] = "HPMCOUNTER28", + [MISCREG_HPMCOUNTER29] = "HPMCOUNTER29", + [MISCREG_HPMCOUNTER30] = "HPMCOUNTER30", + [MISCREG_HPMCOUNTER31] = "HPMCOUNTER31", + [MISCREG_HPMEVENT03] = "HPMEVENT03", + [MISCREG_HPMEVENT04] = "HPMEVENT04", + [MISCREG_HPMEVENT05] = "HPMEVENT05", + [MISCREG_HPMEVENT06] = "HPMEVENT06", + [MISCREG_HPMEVENT07] = "HPMEVENT07", + [MISCREG_HPMEVENT08] = "HPMEVENT08", + [MISCREG_HPMEVENT09] = "HPMEVENT09", + [MISCREG_HPMEVENT10] = "HPMEVENT10", + [MISCREG_HPMEVENT11] = "HPMEVENT11", + [MISCREG_HPMEVENT12] = "HPMEVENT12", + [MISCREG_HPMEVENT13] = "HPMEVENT13", + [MISCREG_HPMEVENT14] = "HPMEVENT14", + [MISCREG_HPMEVENT15] = "HPMEVENT15", + [MISCREG_HPMEVENT16] = "HPMEVENT16", + [MISCREG_HPMEVENT17] = "HPMEVENT17", + [MISCREG_HPMEVENT18] = "HPMEVENT18", + [MISCREG_HPMEVENT19] = "HPMEVENT19", + [MISCREG_HPMEVENT20] = "HPMEVENT20", + [MISCREG_HPMEVENT21] = "HPMEVENT21", + [MISCREG_HPMEVENT22] = "HPMEVENT22", + [MISCREG_HPMEVENT23] = "HPMEVENT23", + [MISCREG_HPMEVENT24] = "HPMEVENT24", + [MISCREG_HPMEVENT25] = "HPMEVENT25", + [MISCREG_HPMEVENT26] = "HPMEVENT26", + [MISCREG_HPMEVENT27] = "HPMEVENT27", + [MISCREG_HPMEVENT28] = "HPMEVENT28", + [MISCREG_HPMEVENT29] = "HPMEVENT29", + [MISCREG_HPMEVENT30] = "HPMEVENT30", + [MISCREG_HPMEVENT31] = "HPMEVENT31", + [MISCREG_TSELECT] = "TSELECT", + [MISCREG_TDATA1] = "TDATA1", + [MISCREG_TDATA2] = "TDATA2", + [MISCREG_TDATA3] = "TDATA3", + [MISCREG_DCSR] = "DCSR", + [MISCREG_DPC] = "DPC", + [MISCREG_DSCRATCH] = "DSCRATCH", + + [MISCREG_MEDELEG] = "MEDELEG", + [MISCREG_MIDELEG] = "MIDELEG", + [MISCREG_MTVEC] = "MTVEC", + [MISCREG_MCOUNTEREN] = "MCOUNTEREN", + [MISCREG_MSCRATCH] = "MSCRATCH", + [MISCREG_MEPC] = "MEPC", + [MISCREG_MCAUSE] = "MCAUSE", + [MISCREG_MTVAL] = "MTVAL", + [MISCREG_PMPCFG0] = "PMPCFG0", + // pmpcfg1 rv32 only + [MISCREG_PMPCFG2] = "PMPCFG2", + // pmpcfg3 rv32 only + [MISCREG_PMPADDR00] = "PMPADDR00", + [MISCREG_PMPADDR01] = "PMPADDR01", + [MISCREG_PMPADDR02] = "PMPADDR02", + [MISCREG_PMPADDR03] = "PMPADDR03", + [MISCREG_PMPADDR04] = "PMPADDR04", + [MISCREG_PMPADDR05] = "PMPADDR05", + [MISCREG_PMPADDR06] = "PMPADDR06", + [MISCREG_PMPADDR07] = "PMPADDR07", + [MISCREG_PMPADDR08] = "PMPADDR08", + [MISCREG_PMPADDR09] = "PMPADDR09", + [MISCREG_PMPADDR10] = "PMPADDR10", + [MISCREG_PMPADDR11] = "PMPADDR11", + [MISCREG_PMPADDR12] = "PMPADDR12", + [MISCREG_PMPADDR13] = "PMPADDR13", + [MISCREG_PMPADDR14] = "PMPADDR14", + [MISCREG_PMPADDR15] = "PMPADDR15", + + [MISCREG_SEDELEG] = "SEDELEG", + [MISCREG_SIDELEG] = "SIDELEG", + [MISCREG_STVEC] = "STVEC", + [MISCREG_SCOUNTEREN] = "SCOUNTEREN", + [MISCREG_SSCRATCH] = "SSCRATCH", + [MISCREG_SEPC] = "SEPC", + [MISCREG_SCAUSE] = "SCAUSE", + [MISCREG_STVAL] = "STVAL", + [MISCREG_SATP] = "SATP", + + [MISCREG_UTVEC] = "UTVEC", + [MISCREG_USCRATCH] = "USCRATCH", + [MISCREG_UEPC] = "UEPC", + [MISCREG_UCAUSE] = "UCAUSE", + [MISCREG_UTVAL] = "UTVAL", + [MISCREG_FFLAGS] = "FFLAGS", + [MISCREG_FRM] = "FRM", +}}; + ISA::ISA(Params *p) : BaseISA(p) { miscRegFile.resize(NumMiscRegs); @@ -105,8 +232,8 @@ ISA::readMiscRegNoEffect(int misc_reg) const panic("Illegal CSR index %#x\n", misc_reg); return -1; } - DPRINTF(RiscvMisc, "Reading MiscReg %d: %#llx.\n", misc_reg, - miscRegFile[misc_reg]); + DPRINTF(RiscvMisc, "Reading MiscReg %s (%d): %#x.\n", + MiscRegNames[misc_reg], misc_reg, miscRegFile[misc_reg]); return miscRegFile[misc_reg]; } @@ -180,7 +307,8 @@ ISA::setMiscRegNoEffect(int misc_reg, RegVal val) // Illegal CSR panic("Illegal CSR index %#x\n", misc_reg); } - DPRINTF(RiscvMisc, "Setting MiscReg %d to %#x.\n", misc_reg, val); + DPRINTF(RiscvMisc, "Setting MiscReg %s (%d) to %#x.\n", + MiscRegNames[misc_reg], misc_reg, val); miscRegFile[misc_reg] = val; }