From: Andrew Waterman <waterman@s144.Millennium.Berkeley.EDU>
Date: Sun, 7 Nov 2010 00:44:56 +0000 (-0700)
Subject: [opcodes] generate latex and verilog correctly
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d443095f92d8ff5d7c9831e1e111ef605d637f0;p=riscv-isa-sim.git

[opcodes] generate latex and verilog correctly
---

diff --git a/riscv/execute.h b/riscv/execute.h
index ae8cfdf..be90e6f 100644
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -31,6 +31,73 @@ switch((insn.bits >> 0x19) & 0x7f)
     #include "insns/jal.h"
     break;
   }
+  case 0x62:
+  {
+    switch((insn.bits >> 0x16) & 0x7)
+    {
+      case 0x0:
+      {
+        #include "insns/jalr_c.h"
+        break;
+      }
+      case 0x1:
+      {
+        #include "insns/jalr_r.h"
+        break;
+      }
+      case 0x2:
+      {
+        #include "insns/jalr_j.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
+    }
+    break;
+  }
+  case 0x63:
+  {
+    switch((insn.bits >> 0x16) & 0x7)
+    {
+      case 0x0:
+      {
+        #include "insns/beq.h"
+        break;
+      }
+      case 0x1:
+      {
+        #include "insns/bne.h"
+        break;
+      }
+      case 0x4:
+      {
+        #include "insns/blt.h"
+        break;
+      }
+      case 0x5:
+      {
+        #include "insns/bge.h"
+        break;
+      }
+      case 0x6:
+      {
+        #include "insns/bltu.h"
+        break;
+      }
+      case 0x7:
+      {
+        #include "insns/bgeu.h"
+        break;
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
+    }
+    break;
+  }
   case 0x68:
   {
     switch((insn.bits >> 0x16) & 0x7)
@@ -629,73 +696,6 @@ switch((insn.bits >> 0x19) & 0x7f)
     #include "insns/lui.h"
     break;
   }
-  case 0x72:
-  {
-    switch((insn.bits >> 0x16) & 0x7)
-    {
-      case 0x0:
-      {
-        #include "insns/jalr_c.h"
-        break;
-      }
-      case 0x1:
-      {
-        #include "insns/jalr_r.h"
-        break;
-      }
-      case 0x2:
-      {
-        #include "insns/jalr_j.h"
-        break;
-      }
-      default:
-      {
-        #include "insns/unimp.h"
-      }
-    }
-    break;
-  }
-  case 0x73:
-  {
-    switch((insn.bits >> 0x16) & 0x7)
-    {
-      case 0x0:
-      {
-        #include "insns/beq.h"
-        break;
-      }
-      case 0x1:
-      {
-        #include "insns/bne.h"
-        break;
-      }
-      case 0x4:
-      {
-        #include "insns/blt.h"
-        break;
-      }
-      case 0x5:
-      {
-        #include "insns/bge.h"
-        break;
-      }
-      case 0x6:
-      {
-        #include "insns/bltu.h"
-        break;
-      }
-      case 0x7:
-      {
-        #include "insns/bgeu.h"
-        break;
-      }
-      default:
-      {
-        #include "insns/unimp.h"
-      }
-    }
-    break;
-  }
   case 0x74:
   {
     switch((insn.bits >> 0x16) & 0x7)