From: Alberto Gonzalez <boqwxp@airmail.cc>
Date: Sun, 19 Apr 2020 22:41:21 +0000 (+0000)
Subject: Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and `cellbits_... 
X-Git-Tag: working-ls180~517^2~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=6d64d768b07a027fff42515dbba4cdb6f060d17a;p=yosys.git

Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and `cellbits_to_tplbits`.
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 96508845d..b4df6142e 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -862,9 +862,9 @@ struct TechmapWorker
 								techmap_do_cache[new_tpl] = true;
 								tpl = new_tpl;
 
-								std::map<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
-								std::map<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
-								std::map<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
+								dict<RTLIL::SigBit, RTLIL::SigBit> port_new2old_map;
+								dict<RTLIL::SigBit, RTLIL::SigBit> port_connmap;
+								dict<RTLIL::SigBit, RTLIL::SigBit> cellbits_to_tplbits;
 
 								for (auto wire : tpl->wires().to_vector())
 								{